Published:2012/10/10 21:32:00 Author:Ecco | Keyword: Level test , TTL, six NOT gate | From:SeekIC
Because TTL ( CMOS ) circuit has determined high, low level input threshold voltage, it does not need additional set or adjust, and the result is very accurate. The two NAND gates of input end can be connected in parallel to increase drive capability, high level dispalys H, low level displays L. Due to they use common anode digital tube, VD1, VD2 polarity needs to be changed. If the CMOS level needs to be tested, you should use CMOS NAND gate circuit 4069.
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