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Part Number: FDC6302P

 

MFG: Fairchild

 

 

Description: These Dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchil...


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FDC6302P General Description


These Dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance.  This  device has been designed especially for low voltage applications as a replacement for digital transistors in load switchimg applications.Since bias resistors are not required this one P-Channel FET
can replace several digital transistors with different bias resistors like the IMBxA series.

FDC6302P Maximum Ratings

Symbol
Parameter
FDC6304P
Units
VDSS
Drain-Source Voltage, Power Supply Voltage
-25
V
VGSS
Gate-Source Voltage,
8
V
ID, IO
Drain Current - Continuous    
                      - Pulsed
 
-0.12
A
-0.5
PD
Maximum Power Dissipation (Note 1a)                      
                                             (Note1b)                                                
0.9
W
0.7
TJ, Tstg
Operating and Storage Tempature Ranger
-55 to +150
°C
ESD
Electrostatic Discharge Rating MIL-STD-883D      
Human Body Model (100pf / 1500 Ohm)        
6
kV

FDC6302P Features

-25 V, -0.12 A continuous, -0.5 A Peak.
         R DS(ON)= 13 W @ VGS= -2.7 V
         R DS(ON) = 10 W@ VGS= -4.5 V
Very low level gate drive requirements allowing  direct operation in 3V circuits. V GS(th)<1.5V.
Gate-Source Zener for ESD ruggedness.>6kV Human Body Model
Replace multiple PNP digital transistors (IMHxA series) with one DMOS FET.

FDC6302P datasheet

FDC6302P
PDF/DataSheet Download

  • Datasheet: FDC6302P
  • File Size: 77843 KB
  • Manufacturer: FAIRCHILD [Fairchild Semiconductor]
  • Click here to Download

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