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The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flipflop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.
74AC175PC Maximum Ratings
Supply Voltage (VCC).................. −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V ......................................... −20 mA VI = VCC + 0.5V................................. +20 mA DC Input Voltage (VI) .........−0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V........................................ −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) ......−0.5V to VCC + 0.5V DC Output Source or Sink Current (IO)............................ ±50 mA DC VCC or Ground Current per Output Pin (ICC or IGND)............... ±50 mA Storage Temperature (TSTG)... −65°C to +150°C Junction Temperature (TJ) PDIP ......................................................140°C
74AC175PC Features
ICC reduced by 50% Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous common reset True and complement output Outputs source/sink 24 mA ACT175 has TTL-compatible inputs
74AC175PC Connection Diagram
74AC175SC Parameters
Technical/Catalog Information
74AC175SC
Vendor
Fairchild Semiconductor
Category
Integrated Circuits (ICs)
Mounting Type
Surface Mount
Package / Case
16-SO
Function
Master Reset
Number of Bits per Element
4
Number of Elements
1 - Single
Current - Output High, Low
24mA, 24mA
Output Type
Differential
Trigger Type
Positive Edge
Type
D-Type Bus
Packaging
Tube
Operating Temperature
-40°C ~ 85°C
Delay Time - Propagation
7ns
Frequency - Clock
244MHz
Voltage - Supply
2 V ~ 6 V
Lead Free Status
Lead Free
RoHS Status
RoHS Compliant
Other Names
74AC175SC 74AC175SC
74AC175SC General Description
The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flipflop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.
74AC175SC Maximum Ratings
Supply Voltage (VCC).................. −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V ......................................... −20 mA VI = VCC + 0.5V................................. +20 mA DC Input Voltage (VI) .........−0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V........................................ −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) ......−0.5V to VCC + 0.5V DC Output Source or Sink Current (IO)............................ ±50 mA DC VCC or Ground Current per Output Pin (ICC or IGND)............... ±50 mA Storage Temperature (TSTG)... −65°C to +150°C Junction Temperature (TJ) PDIP ......................................................140°C
74AC175SC Features
ICC reduced by 50% Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous common reset True and complement output Outputs source/sink 24 mA ACT175 has TTL-compatible inputs
