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74LS165N, 74LS165PC, 74LS166

Table of contents:
Info of 74LS165N
Info of 74LS165PC
Info of 74LS166

74LS165N, 74LS165PC, 74LS166 Selling Leads, Datasheet

MFG:MOT Package Cooled:DIP-16 D/C:02+

74LS165N, 74LS165PC, 74LS166 Datasheet download

Five Points

Part Number: 74LS165N

MFG: MOT

Package Cooled: DIP-16

D/C: 02+

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74LS166 General Description

The SN54L/74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified.

The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.

74LS166 Features

• Synchronous Load
• Direct Overriding Clear
• Parallel to Serial Conversion

74LS166 Connection Diagram

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