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74LVC06, 74LVC06(SMDSN74LVC06AD)D/C01, 74LVC06A

Table of contents:
Info of 74LVC06
Info of 74LVC06(SMDSN74LVC06AD)D/C01
Info of 74LVC06A

74LVC06, 74LVC06(SMDSN74LVC06AD)D/C01, 74LVC06A Selling Leads, Datasheet

MFG:TI Package Cooled:SOP D/C:07+

74LVC06, 74LVC06(SMDSN74LVC06AD)D/C01, 74LVC06A Picture

74LVC06, 74LVC06(SMDSN74LVC06AD)D/C01, 74LVC06A Datasheet download

Five Points

Part Number: 74LVC06

MFG: TI

Package Cooled: SOP

D/C: 07+

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74LVC06A General Description

The 74LVC06A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 to 5 V environment.
The 74LVC06A provides six inverting buffers.

The outputs of the 74LVC06A devices are open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

74LVC06A Maximum Ratings

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
V_CC	DC supply voltage		-0.5	+6.5	V
I_IK	DC input diode current	V_I<0	-	-50	mA
V_I	DC input voltage	note 1	-0.5	+6.5	V
I_OK	DC output clamping diode current	VO <0	-	-50	mA
V_O	DC output voltage	active mode; note 1	-0.5	VCC + 0.5	V
V_O	DC output voltage	high-impedance mode; note 1	-0.5	+6.5	V
L_O	DC output sink current	VO = 0 to V_CC	-	50	mA
I_CC, I_GND	DC V_CC or GND current		-	±100	mA
T_stg	storage temperature		-65	±150	°C
Ptot	power dissipation per package SO package TSSOP package	above 70 °C derate linearly with 8 mW/K above 60 °C derate linearly with 5.5 mW/K	- -	500 500	mW mW

74LVC06A Features

· 5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
· Wide supply voltage range from 1.65 to 5.5 V
· CMOS low power consumption
· Direct interface with TTL levels
· Inputs accept voltages up to 5 V
· Complies with JEDEC standard no. 8-1A.

74LVC06A Connection Diagram

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