74LVC2G00DC-G, 74LVC2G00DP 125, 74LVC2G02 Selling Leads, Datasheet
MFG:NXP Package Cooled:tssop/3k/
74LVC2G00DC-G, 74LVC2G00DP 125, 74LVC2G02 Datasheet download
Part Number: 74LVC2G00DC-G
MFG: NXP
Package Cooled: tssop/3k/
D/C:
74LVC2G00DC-G, 74LVC2G00DP 125, 74LVC2G02
- Table of contents:
Info of 74LVC2G00DC-G
Info of 74LVC2G00DP 125
Info of 74LVC2G02
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About 74L71
PDF/DataSheet Download
Datasheet: 74L71
File Size: 105703 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
About 74L71
PDF/DataSheet Download
Datasheet: 74L71
File Size: 105703 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
About 74LVC2G02
PDF/DataSheet Download
Datasheet: 74LVC2G02
File Size: 93882 KB
Manufacturer: PANASONIC [Panasonic Semiconductor]
Download : Click here to Download
74LVC2G02 General Description
The 74LVC2G02 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC2G02 provides the 2-input NOR gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC2G02 provides the 2-input NOR gate function.
74LVC2G02 Maximum Ratings
| SYMBOL | PARAMETER | CONDITIONS | MIN. | MAX. | UNIT |
| VCC | supply voltage | -0.5 | +6.5 | V | |
| IIK | input diode current | VI< 0 | - | -50 | mA |
| VI | input voltage | note 1 | -0.5 | +6.5 | V |
| IOK | output diode current | VO> VCC or VO< 0 V | - | ±50 | mA |
| VO | output voltage | active mode; notes 1 and 2 | -0.5 | VCC+0.5 | V |
| Power-down mode; notes 1 and 2 | -0.5 | +6.5 | V | ||
| IO | output source or sink current | VO = 0 V to VCC | - | ±50 | mA |
| ICC, IGND | VCC or GND current | - | ±100 | mA | |
| Tstg | storage temperature | -65 | +150 | °C | |
| PD | power dissipation | Tamb = -40 °C to +125 °C | - | 300 | mW |
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
74LVC2G02 Features
` Wide supply voltage range from 1.65 V to 5.5 V
` 5 V tolerant outputs for interfacing with 5 V logic
` High noise immunity
` Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
` ±24 mA output drive (VCC = 3.0 V)
` CMOS low power consumption
` Latch-up performance exceeds 250 mA
` Direct interface with TTL levels
` Inputs accept voltages up to 5 V
` Multiple package options
` ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
` Specified from -40 °C to +85 °C and -40 °C to +125 °C.
` 5 V tolerant outputs for interfacing with 5 V logic
` High noise immunity
` Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
` ±24 mA output drive (VCC = 3.0 V)
` CMOS low power consumption
` Latch-up performance exceeds 250 mA
` Direct interface with TTL levels
` Inputs accept voltages up to 5 V
` Multiple package options
` ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
` Specified from -40 °C to +85 °C and -40 °C to +125 °C.
74LVC2G02 Connection Diagram
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