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The AD9925 is a complete 36 MHz front end solution for digi-tal still camera and other CCD imaging applications. Based on the AD9995 product, the AD9925 includes the analog front end and a fully programmable timing generator (AFETG), combined with a 10-channel vertical driver (V-driver). A Precision Timing core allows adjustment of high speed clocks with approximately 600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 10 channels for use with 3-field (6-phase) CCDs. Two additional vertical outputs can be used with CCDs that contain advanced video readout modes. Voltage levels of up to +15 V and −8 V are supported.
The analog front end includes black level clamping, CDS, VGA, and a 12-bit ADC. The timing generator and V-driver provide all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor gate pulses, substrate clock, and substrate bias control. The internal registers are programmed using a 3-wire serial interface.
Packaged in an 8 mm × 8 mm CSPBGA, the AD9925 is speci-fied over an operating temperature range of −25°C to +85°C.
AD9925 Maximum Ratings
Parameter
With Respect To
Min
Max
Unit
VDD
VDVSS
VDVSS − 0.3
VDVSS + 4
V
VL
VDVSS
VDVSS − 10.0
VDVSS + 0.3
V
VH1, VH2
VDVSS
VL 0.3
VL + 27.0
V
VM1, VM2
VDVSS
VL 0.3
VL + 27.0
V
AVDD
AVSS
−0.3
+3.9
V
TCVDD
TCVSS
−0.3
+3.9
V
HVDD
HVSS
−0.3
+3.9
V
RGVDD
RGVSS
−0.3
+3.9
V
DVDD
DVSS
−0.3
+3.9
V
DRVDD
DRVSS
−0.3
+3.9
V
RG Output
RGVSS
−0.3
RGVDD + 0.3
V
H1 to H2 Output
HVSS
−0.3
HVDD + 0.3
V
Digital Outputs
DVSS
−0.3
DVDD + 0.3
V
Digital Inputs
DVSS
−0.3
DVDD + 0.3
V
SCK, SL, SDATA
DVSS
−0.3
DVDD + 0.3
V
REFT/REFB, CCDIN
AVSS
−0.3
AVDD + 0.3
V
Junction Tempera-ture
150
°C
Lead Temperature, 10 s
350
°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD9925 Features
Integrated 10-channel V-driver Register-compatible with the AD9991 and AD9995 3-field (6-phase) vertical clock support 2 additional vertical outputs for advanced CCDs Complete on-chip timing generator Precision Timing core with <600 ps resolution Correlated double sampler (CDS) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit 36 MHz ADC Black level clamp with variable level control On-chip 3 V horizontal and RG drivers 2-phase and 4-phase H-clock modes Electronic and mechanical shutter support On-chip driver for external crystal On-chip sync generator with external sync input 8 mm × 8 mm CSPBGA package with 0.65 mm pitch
AD9925 Typical Application
Digital still cameras Digital video camcorders CCD camera modules