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The ADSP-TS201S TigerSHARC processor is an ultra-high performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks-supporting 32- and 40-bit floating-point and supporting 8-, 16-, 32-, and 64-bit fixed-point processing-to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing twenty-four 16-bit fixed-point operations or six floating-point operations.
Four independent 128-bit wide internal data buses, each connecting to the six 4M bit memory banks, enable quad-word data, instruction, and I/O accesses and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS201S processor's core has a 2.0 ns instruction cycle time. Using its Single-Instruction, Multiple-Data (SIMD) features, the ADSP-TS201S processor can perform four billion 40-bit MACs or one billion 80-bit MACs per second. Table 1 shows the DSP's performance benchmarks.
ADSP-TS201S Maximum Ratings
Internal (Core) Supply Voltage (VDD)1 . . . . . . . . . . 0.3 V to +1.40 V Analog (PLL) Supply Voltage (VDD_A)1 . . . . . . . . . . 0.3 V to +1.40 V External (I/O) Supply Voltage (VDD_IO)1 . . . . . . . . . .0.3 V to +3.5 V External (DRAM) Supply Voltage (VDD_DRAM)1 . . . . . 0.3 V to +2.1 V Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 3.63 V Output Voltage Swing1 . . . . . . . . . . . . . . . . . 0.5 V to VDD_IO+0.5 V Storage Temperature Range1 . . . . . . . . . . . . . . . . . 65ºC to +150ºC 1 Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADSP-TS201S Features
` 500 MHz, 2.0 ns Instruction Cycle Rate ` 24M Bits of Internal-On-Chip-DRAM Memory ` 2525 mm (576-Ball) Thermally Enhanced Ball Grid ` Array Package ` Dual Computation Blocks-Each Containing an ALU, a ` Multiplier, a Shifter, a Register File, and a ` Communications Logic Unit (CLU) ` Dual Integer ALUs, providing Data Addressing and ` Pointer Manipulation ` Integrated I/O Includes 14 Channel DMA Controller, ` External Port, Four Link Ports, SDRAM Controller, ` Programmable Flag Pins, Two Timers, and Timer ` Expired Pin for System Integration ` 1149.1 IEEE Compliant JTAG Test Access Port for On- ` Chip Emulation ` On-Chip Arbitration for Glueless Multiprocessing