ADSP2101Y, ADSP-21020, ADSP-2102020020ED Selling Leads, Datasheet
MFG:ADI Package Cooled:N/A D/C:09+
ADSP2101Y, ADSP-21020, ADSP-2102020020ED Datasheet download
Part Number: ADSP2101Y
MFG: ADI
Package Cooled: N/A
D/C: 09+
ADSP2101Y, ADSP-21020, ADSP-2102020020ED
- Table of contents:
Info of ADSP2101Y
Info of ADSP-21020
Info of ADSP-2102020020ED
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About ADS1100
PDF/DataSheet Download
Datasheet: ADS1100
File Size: 189503 KB
Manufacturer: BURR-BROWN [Burr-Brown Corporation]
Download : Click here to Download
About ADSP-21020
PDF/DataSheet Download
Datasheet: ADSP-21020
File Size: 531879 KB
Manufacturer:
Download : Click here to Download
About ADS1100
PDF/DataSheet Download
Datasheet: ADS1100
File Size: 189503 KB
Manufacturer: BURR-BROWN [Burr-Brown Corporation]
Download : Click here to Download
ADSP-21020 General Description
The ADSP-21020 is the first member of Analog Devices' family of single-chip IEEE floating-point processors optimized for digital signal processing applications. Its architecture is similar to that of Analog Devices' ADSP-2100 family of fixed-point DSP processors.
Fabricated in a high-speed, low-power CMOS process, the ADSP-21020 has a 30 ns instruction cycle time. With a highperformance on-chip instruction cache, the ADSP-21020 can execute every instruction in a single cycle.
ADSP-21020 Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . .. . .0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . . .0.3 V to VDD + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 200 pF
Operating Temperature Range (Ambient) . . 55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .65°C to +150°C
Lead Temperature (10 seconds) CPGA . . . . . . . . . . . . .+300°C
Input Voltage . . . . . . . . . . . . . . . . . . . .. . .0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . . .0.3 V to VDD + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 200 pF
Operating Temperature Range (Ambient) . . 55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .65°C to +150°C
Lead Temperature (10 seconds) CPGA . . . . . . . . . . . . .+300°C
ADSP-21020 Features
Superscalar IEEE Floating-Point Processor
Off-Chip Harvard Architecture Maximizes Signal Processing Performance
30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution
100 MFLOPS Peak, 66 MFLOPS Sustained Performance
1024-Point Complex FFT Benchmark: 0.58 ms
Divide (y/x): 180 ns
Inverse Square Root (1/x): 270 ns
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats
32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators
IEEE Exception Handling with Interrupt on Exception
Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter
Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes
Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply & ALU Operations
Multiply with Add & Subtract for FFT Butterfly Computation
Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup
Single-Cycle Register File Context Switch
15 (or 25) ns External RAM Access Time for Zero-Wait- State, 30 (or 40) ns Instruction Execution
IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation Circuitry
223-Pin PGA Package (Ceramic)
Off-Chip Harvard Architecture Maximizes Signal Processing Performance
30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution
100 MFLOPS Peak, 66 MFLOPS Sustained Performance
1024-Point Complex FFT Benchmark: 0.58 ms
Divide (y/x): 180 ns
Inverse Square Root (1/x): 270 ns
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats
32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators
IEEE Exception Handling with Interrupt on Exception
Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter
Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes
Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply & ALU Operations
Multiply with Add & Subtract for FFT Butterfly Computation
Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup
Single-Cycle Register File Context Switch
15 (or 25) ns External RAM Access Time for Zero-Wait- State, 30 (or 40) ns Instruction Execution
IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation Circuitry
223-Pin PGA Package (Ceramic)
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