ADSP2187KST210, ADSP-2187KST-210, ADSP-2187L Selling Leads, Datasheet
MFG:QFP Package Cooled:AD D/C:09+
ADSP2187KST210, ADSP-2187KST-210, ADSP-2187L Datasheet download
Part Number: ADSP2187KST210
MFG: QFP
Package Cooled: AD
D/C: 09+
ADSP2187KST210, ADSP-2187KST-210, ADSP-2187L
- Table of contents:
Info of ADSP2187KST210
Info of ADSP-2187KST-210
Info of ADSP-2187L
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About ADS1100
PDF/DataSheet Download
Datasheet: ADS1100
File Size: 189503 KB
Manufacturer: BURR-BROWN [Burr-Brown Corporation]
Download : Click here to Download
About ADS1100
PDF/DataSheet Download
Datasheet: ADS1100
File Size: 189503 KB
Manufacturer: BURR-BROWN [Burr-Brown Corporation]
Download : Click here to Download
About ADSP-2187L
PDF/DataSheet Download
Datasheet: ADSP-2187L
File Size: 231740 KB
Manufacturer:
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ADSP-2187L General Description
The ADSP-2187L is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2187L combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory.
The ADSP-2187L integrates 160K bytes of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2187L is available in 100-lead TQFP package.
In addition, the ADSP-2187L supports new instructions, which include bit manipulations-bit set, bit clear, bit toggle, bit test- new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking, for increased flexibility.
Fabricated in a high speed, low power, CMOS process, the ADSP-2187L operates with a 19 ns instruction cycle time. Every instruction can execute in a single processor cycle.
ADSP-2187L Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) .. 40°C to +85°C
Storage Temperature Range . . . . . . . . . . 65°C to +150°C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADSP-2187L Features
PERFORMANCE
`19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
`Sustained Performance
`Single-Cycle Instruction Execution
`Single-Cycle Context Switch
`3-Bus Architecture Allows Dual Operand Fetches in
`Every Instruction Cycle
`Multifunction Instructions
`Power-Down Mode Featuring Low CMOS Standby
`Power Dissipation with 400 Cycle Recovery from
`Power-Down Condition
`Low Power Dissipation in Idle Mode
INTEGRATION
`ADSP-2100 Family Code Compatible, with Instruction
`Set Extensions
`160K Bytes of On-Chip RAM, Configured as 32K Words
`Program Memory RAM and 32K Words
`Data Memory RAM
`Dual Purpose Program Memory for InstructionÊ and Data Storage
`Independent ALU, Multiplier/Accumulator and Barrel
`Shifter Computational Units
`Two Independent Data Address Generators
`Powerful Program Sequencer Provides Zero Overhead
`Looping Conditional Instruction Execution
`Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP
SYSTEM INTERFACE
`16-Bit Internal DMA Port for High Speed Access to
`On-Chip Memory (Mode Selectable)
`4 MByte Memory Interface for Storage of Data Tables and Program Overlays (Mode Selectable)
`8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)
`I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable)
`Programmable Memory Strobe and Separate I/O Memory
`Space Permits "Glueless" System Design
`Programmable Wait State Generation
`Two Double-Buffered Serial Ports with Companding
`Hardware and Automatic Data Buffering
`Automatic Booting of On-Chip Program Memory from
`Byte-Wide External Memory, e.g., EPROM, or
`Through Internal DMA Port
`Six External Interrupts
`13 Programmable Flag Pins Provide Flexible System
`Signaling
`UART Emulation through Software SPORT Reconfiguration
`ICE-Port™ Emulator Interface Supports Debugging in
`Final Systems
`19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
`Sustained Performance
`Single-Cycle Instruction Execution
`Single-Cycle Context Switch
`3-Bus Architecture Allows Dual Operand Fetches in
`Every Instruction Cycle
`Multifunction Instructions
`Power-Down Mode Featuring Low CMOS Standby
`Power Dissipation with 400 Cycle Recovery from
`Power-Down Condition
`Low Power Dissipation in Idle Mode
INTEGRATION
`ADSP-2100 Family Code Compatible, with Instruction
`Set Extensions
`160K Bytes of On-Chip RAM, Configured as 32K Words
`Program Memory RAM and 32K Words
`Data Memory RAM
`Dual Purpose Program Memory for InstructionÊ and Data Storage
`Independent ALU, Multiplier/Accumulator and Barrel
`Shifter Computational Units
`Two Independent Data Address Generators
`Powerful Program Sequencer Provides Zero Overhead
`Looping Conditional Instruction Execution
`Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP
SYSTEM INTERFACE
`16-Bit Internal DMA Port for High Speed Access to
`On-Chip Memory (Mode Selectable)
`4 MByte Memory Interface for Storage of Data Tables and Program Overlays (Mode Selectable)
`8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)
`I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable)
`Programmable Memory Strobe and Separate I/O Memory
`Space Permits "Glueless" System Design
`Programmable Wait State Generation
`Two Double-Buffered Serial Ports with Companding
`Hardware and Automatic Data Buffering
`Automatic Booting of On-Chip Program Memory from
`Byte-Wide External Memory, e.g., EPROM, or
`Through Internal DMA Port
`Six External Interrupts
`13 Programmable Flag Pins Provide Flexible System
`Signaling
`UART Emulation through Software SPORT Reconfiguration
`ICE-Port™ Emulator Interface Supports Debugging in
`Final Systems
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