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AM29LV080BT-90EI, AM29LV081, AM29LV081-120

Table of contents:
Info of AM29LV080BT-90EI
Info of AM29LV081
Info of AM29LV081-120

AM29LV080BT-90EI, AM29LV081, AM29LV081-120 Selling Leads, Datasheet

MFG:AMD Package Cooled:TSOP D/C:D/C

AM29LV080BT-90EI, AM29LV081, AM29LV081-120 Picture

AM29LV080BT-90EI, AM29LV081, AM29LV081-120 Datasheet download

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Part Number: AM29LV080BT-90EI

MFG: AMD

Package Cooled: TSOP

D/C: D/C

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AM29LV081 General Description

The Am29LV081 is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes. The device is offered in a 40-pin TSOP package. The byte-wide (x8) data appears on DQ7DQ0. This device requires only a single, 3.0 volt V_CC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm- an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V_CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This is achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation bin progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

AM29LV081 Maximum Ratings

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . 65 to +150
Ambient Temperature
with Power Applied. . . . . . . . . . . . . 65 to +125
Voltage with Respect to Ground
V_CC(Note 1) . . . . . . . . . . . . . ..... . .0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . ...... . .0.5 V to +12.5 V
All other pins (Note 1) . . . . ...... 0.5 V to V_CC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may
   undershoot V_SS to 2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on input or I/O
   pins is V_CC +0.5 V. During voltage transitions, input or I/O pins may overshoot to V_CC +2.0 V for periods up
   to 20 ns. See Figure 7.

2. Minimum DC input voltage on pins A9, OE#, and RESET# is 0.5 V. During voltage transitions, A9, OE#,
    and RESET# may undershoot V_SS to 2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input
    voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be
greater than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

AM29LV081 Features

` Optimized architecture for Miniature Card and mass storage applications
`Single power supply operation
   - Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
   - Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high
      performance 3.3 volt microprocessors
` High performance
    - Full voltage range: access times as fast as 100 ns
    - Regulated voltage range: access times as fast as 90 ns
` Ultra low power consumption (typical values at 5 MHz)
    - 200 nA Automatic Sleep mode current
    - 200 nA standby mode current
    - 10 mA read current
    - 20 mA program/erase current
` Flexible sector architecture
    - Sixteen 64 Kbyte sectors
    - Supports full chip erase
    - Sector Protection features: A hardware method of locking a sector (using programming equipment) to
       prevent any program or erase operations within that sector Temporary Sector Unprotect feature allows
        code changes in previously locked sectors
` Embedded Algorithms
    - Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination
       of designated sectors
    - Embedded Program algorithm automatically writes and verifies data at specified addresses
` Typical 1,000,000 write cycles per sector (100,000 cycles minimum guaranteed)
` Package option
    - 40-pin TSOP
` Compatibility with JEDEC standards
    - Pinout and software compatible with singlepower supply Flash
    - Superior inadvertent write protection
` Data# Polling and toggle bits
    - Provides a software method of detecting program or erase operation completion
` Ready/Busy# pin (RY/BY#)
    - Provides a hardware method of detecting program or erase cycle completion
` Erase Suspend/Erase Resume
    - Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
` Hardware reset pin (RESET#)
    - Hardware method to reset the device to reading array data

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