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CAT28F102, CAT28F102AN12, CAT28F102FN-90

CAT28F102, CAT28F102AN12, CAT28F102FN-90 Selling Leads, Datasheet

MFG:CSI  Package Cooled:PLCC  D/C:PLCC

CAT28F102, CAT28F102AN12, CAT28F102FN-90 Picture

CAT28F102, CAT28F102AN12, CAT28F102FN-90 Datasheet download

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Part Number: CAT28F102

 

MFG: CSI

Package Cooled: PLCC

D/C: PLCC

 

 

 
 
 
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  • CAT28F102FN-90

  • Vendor: CSI Pack: PLCC D/C: 06+& Qty: 1500 Note: ,,  Adddate: 2024-03-29
  • Inquire Now
  •   China
    Contact: Ms.Miss WANG  
    Tel: 86-021-61327535
    Fax: 86-021-51560779
    (81)

About CAT28F102

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Datasheet: CAT28F102

File Size: 162974 KB

Manufacturer: CATALYST [Catalyst Semiconductor]

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CAT28F102AN12 Suppliers

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About CAT102

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Datasheet: CAT102

File Size: 83422 KB

Manufacturer: CATALYST [Catalyst Semiconductor]

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CAT28F102FN-90 Suppliers

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  • CAT28F102FN-90

  • Vendor: CSI Pack: PLCC D/C: 06+& Qty: 1500 Note: ,,  Adddate: 2024-03-29
  • Inquire Now
  •   China
    Contact: Ms.Miss WANG  
    Tel: 86-021-61327535
    Fax: 86-021-51560779
    (81)

About CAT102

PDF/DataSheet Download

Datasheet: CAT102

File Size: 83422 KB

Manufacturer: CATALYST [Catalyst Semiconductor]

Download : Click here to Download

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CAT28F102 General Description

The CAT28F102 is a high speed 64K x 16-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second.

It is pin and Read timing compatible with standard EPROM and E2PROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation.

The CAT28F102 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP packages.

CAT28F102 Maximum Ratings

Temperature Under Bias ............................................... .... 55°C to +95°C
Storage Temperature ...................................................... 65°C to +150°C
Voltage on Any Pin with Respect to Ground(1) ............ 0.6V to +VCC + 2.0V
Voltage on Pin A9 with Respect to Ground(1) ....................... 2.0V to +13.5V
VPP with Respect to Ground during Program/Erase(1) ......... 0.6V to +14.0V
VCC with Respect to Ground(1) ............................................. .2.0V to +7.0V
Package Power Dissipation Capability (TA = 25°C) ............................... 1.0 W
Lead Soldering Temperature (10 secs) ................................................ 300°C
Output Short Circuit Current(2) ........................................................... 100 mA

CAT28F102 Features

 Fast Read Access Time: 45/55/70/90 ns
  Low Power CMOS Dissipation:
        Active: 30 mA max (CMOS/TTL levels)
        Standby: 1 mA max (TTL levels)
        Standby: 100 mA max (CMOS levels)
  High Speed Programming:
        10 ms per byte
        1 Sec Typ Chip Program
  0.5 Seconds Typical Chip-Erase
 12.0V ± 5% Programming and Erase Voltage
 Commercial,Industrial and Automotive Temperature Ranges
  64K x 16 Word Organization
  Stop Timer for Program/Erase
 On-Chip Address and Data Latches
  JEDEC Standard Pinouts:
        40-pin DIP
        44-pin PLCC
        40-pin TSOP
  100,000 Program/Erase Cycles
  10 Year Data Retention
  Electronic Signature

CAT28F102 Connection Diagram

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