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CD74AC10, CD74AC109, CD74AC109M

Table of contents:
Info of CD74AC10
Info of CD74AC109
Info of CD74AC109M

CD74AC10, CD74AC109, CD74AC109M Selling Leads, Datasheet

MFG:. Package Cooled:DIP D/C:96

CD74AC10, CD74AC109, CD74AC109M Datasheet download

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Part Number: CD74AC10

MFG: .

Package Cooled: DIP

D/C: 96

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CD74AC10 Parameters

CD74AC10 Features

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

CD74AC10 General Description

Triple 3-Input NAND Gates

CD74AC10 Maximum Ratings

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . .. .±50mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O> -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . .±50mA
DC V_CC or Ground Current, I_CC or I_GND (Note 3) . . . . . . . .±100mA

CD74AC10 Features

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

CD74AC10 Typical Application

CD74AC10 Datasheet

CD74AC10 Connection Diagram

CD74AC109 Parameters

CD74AC109 Features

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

CD74AC109 General Description

Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset

CD74AC109 Features

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

CD74AC109 Typical Application

CD74AC109 Datasheet

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