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CD74FCT2827ATQM, CD74FCT2952AM, CD74FCT373

Table of contents:
Info of CD74FCT2827ATQM
Info of CD74FCT2952AM
Info of CD74FCT373

CD74FCT2827ATQM, CD74FCT2952AM, CD74FCT373 Selling Leads, Datasheet

MFG:HAR Package Cooled:SOP-7.2 D/C:ORIGINAL

CD74FCT2827ATQM, CD74FCT2952AM, CD74FCT373 Picture

CD74FCT2827ATQM, CD74FCT2952AM, CD74FCT373 Datasheet download

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Part Number: CD74FCT2827ATQM

MFG: HAR

Package Cooled: SOP-7.2

D/C: ORIGINAL

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CD74FCT373 General Description

The CD74FCT373 is an octal, transparent, D-type latch with 3-state outputs using a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below V_CC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V_CC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The outputs are transparent to the inputs when latch enable (LE) is high. When LE is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. The latch operation is independent of output-enable (OE) input.

OE can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. When OE is high, the outputs are in the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT373 is characterized for operation from 0°C to 70°C.

CD74FCT373 Maximum Ratings

DC supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6 V
DC input clamp current, I_IK (V_I< 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
DC output clamp current, I_OK (V_O< 0.5 V) . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .50 mA
DC output sink current per output pin, I_OL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .70 mA
DC output source current per output pin, I_OH . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . .30 mA
Continuous current through V_CC, I_CC . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 mA
Continuous current through GND . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. .400 mA
Package thermal impedance, _JA (see Note 1) E package) . .. . . . . . . . . . . . . . . . .. .69°C/W
M package) . . . . . . . . . . . . . . . . . . . . 58°C/W
SM package) . . . . . . . . . . . . . . . . . .70°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 65°C to 150°C

CD74FCT373 Features

BiCMOS Technology With Low Quiescent Power
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From V_CC
48-mA Output Sink Current
Controlled Output Edge Rates
Output Voltage Swing Limited to 3.7 V at V_CC = 5 V
SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP

CD74FCT373 Connection Diagram

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