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The 'HC164 and 'HCT164 are 8-bit serial-in parallel-out shiftregisters with asynchronous reset. Data is shifted on thepositive edge of Clock (CP). A LOW on the Master Reset(MR) pin resets the shift register and all outputs go to theLOW state regardless of the input conditions. Two SerialData inputs (DS1 and DS2) are provided, either one can beused as a Data Enable control.
CD74HC164 Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, II For VI< -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO< -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . .±25mA DC VCCor Ground Current, ICCorIGND. . . . . . . . . . . . . . . . . .±50mA
CD74HC164 Features
Buffered Inputs Asynchronous Master Reset Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25 Fanout (Over Temperature Range) - Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55 to 125 Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTLLogic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH= 30% of VCCat V = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH= 2V (Min) - CMOS Input Compatibility, I1 1UAatVOL,VOH