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CXD1957AQ, CXD1958Q, CXD1959R

Table of contents:
Info of CXD1957AQ
Info of CXD1958Q
Info of CXD1959R

CXD1957AQ, CXD1958Q, CXD1959R Selling Leads, Datasheet

MFG:SONY Package Cooled:QFP D/C:07+

CXD1957AQ, CXD1958Q, CXD1959R Datasheet download

Five Points

Part Number: CXD1957AQ

MFG: SONY

Package Cooled: QFP

D/C: 07+

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CXD1958Q General Description

The CXD1958Q is an integrated TCM/QAM demodulator for MMDS systems using the DAVIC MMDS standard. This highly integrated device incorporates an internal 8-bit ADC, image rejection and root-raised cosine filters, all-digital symbol timing recovery PLL, adaptive decision feedback equalizer (DFE) with 10 feedforward and 30 feedback taps, 4-D TCM decoder, and DAVIC/DVB compliant forward error correction comprising (204,188) Reed Solomon decoder, a programmable de-interleaver with I = 12 and I = 204, and a de-randomiser. All internal clocks are generated from a single external 30MHz reference crystal.

Device functionality also includes 3-wire bus interface for configuring up to 2 tuner synthesizers, a sigma delta tuner IF-AGC output, a user programmable RFAFC sigma delta output, spectrum inversion of the received signal for tuner compatibility, and a highly configurable MPEG2-TS interface. An I2C bus interface provides on-board configuration and status monitoring of various functions including access to the equalizer tap values and constellation points. JTAG provides boundary scan test compatibility.

CXD1958Q Maximum Ratings

Description	Symbol	Condition	MIN.	MAX.	UNIT
Digital power supply	DV_DD		DV_ss 0.5	+4.6	V
Analog power supply	AV_DD		AV_ss 0.5	+4.6	V
Input voltage: 3.3V only input pins Input voltage: 5V tolerant input pins	V_I	Pins TRST, TDI, TMS, TCK, A1,A0, VRT, VIN, VRB, XTALI Pins SCL, SDA, RESETN, TEN, TCLK, TDATA, TWR_N,TSDISABLE, DT[9:0]	DV_ss 0.5 DV_ss 0.5	DV_DD + 0.5 DV_SS + 5.5	V
Output voltage: 3.3V only pins Output voltage: 5V tolerant input pins	V_O	Pins TEVAL[9:0], TDO, TVALID, TSLOCK, TSERR, TSDATA[7:0], TSCLK, TSSYNC, XTALO, DTCLK, AGC, RFAGC, VRTS, VRBS Pins INTRPTN, SEN0, SEN1, SCLK, SDATA, SDA, DT[9:0]	DV_ss 0.5 DV_ss 0.5	DV_DD + 0.5 DV_SS + 5.5	V
Storage temperature	T_STG		55	+150	°C

CXD1958Q Features

• DAVIC MMDS V1.1 and V1.3 compliant
• Supports 16, 64 and 256QAM
• Supports 16, 64 and 256 TCM
• Internal 8-bit ADC
• Interface for 10-bit external ADC
• 36.125MHz nominal IF input
• Symbol rate range 5 5.304Mbaud in 6MHz channels
• Integrated matched filtering with 0.15 roll-off factor
• ±400KHz internal carrier offset compensation with negligible losses @ 5Mbaud 6MHz channel
• Symbol timing loop designed to acquire with large offsets. Negligible losses for ±100ppm offsets
• All internal clocks derived from single fixed frequency crystal (30MHz)
• Supports fast re-acquisition mode
• 6s echo cancellation @ 5Mbaud
• Constellation points and equalizer tap values readable via I2C bus
• C/N estimation readable via I2C bus
• Low implementation loss for AWGN only:
0.5dB @ 64QAM (using internal 8-bit A/D);
0.3dB @ 256QAM (excluding A/D);
measured at BER of 3x104 Pre R/S
• I = 12 and I = 204 de-interleaving
• Fast I²C bus compatible control interface
• Tuner IF-AGC output
• User programmable tuner RF-AGC output
• Dedicated 3-wire bus interface to configure up to 2 tuner synthesizers
• 3.3V CMOS technology
• Supports JTAG boundary scan
• 100-pin QFP package

CXD1958Q Typical Application

MMDS set-top boxes

CXD1958Q Connection Diagram

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