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The CXP87240A/87248A is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, VISS/VASS circuit, 32kHz timer/event counter, remote control receiving circuit, general purpose prescaler, HSYNC counter, VCR vertical sync separation circuit and the measuring circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP87240A/87248A provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32kHz operation.
CXP87240A Features
• A wide instruction set (213 instructions) which cover various types of data - 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle During operation 333ns/12MHz (3.0 to 5.5V) During operation 250ns/16MHz (4.5 to 5.5V) During operation 122µs/32kHz • Incorporated ROM capacity 40Kbytes (CXP87240A), 48Kbytes (CXP87248A) • Incorporated RAM capacity 1376bytes • Peripheral functions - A/D converter 8-bit, 12-channel, successive approximation system (Conversion time 20.0µs/16MHz) - Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer) 1-channel - Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter - High precision timing pattern generator PPG 19-pin 32-stage programmable RTG 5-pin 2-channel - PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz) DA gate pulse output 13-bit, 4-channel - Servo input control Capstan FG, Drum FG/PG, CTL input - VSYNC separator - FRC capture unit Incorporated 26-bit and 8-stage FIFO - PWM output 14-bit, 1-channel - VISS/VASS circuit Pulse duty auto detection circuit - Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO - General purpose prescaler 7-bit (SYNC1 input frequency divided, FRC capture possible) - HSYNC counter 12-bit event counter (counts the SYNC1 input.) • Interruption 22 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP • Piggyback/evaluation chip CXP87200A 100-pin ceramic QFP/LQFP