The CY7C138 and CY7C139 are high-speed CMOS 4K x 8　and 4K x 9 dual-port static RAMs. Various arbitration schemes　are included on the CY7C138/9 to handle situations when multiple　processors access the same piece of data. Two ports are　provided permitting independent, asynchronous access for　reads and writes to any location in memory. The CY7C138/9　can be utilized as a standalone 8/9-bit dual-port static RAM or　multiple devices can be combined in order to function as a　16/18-bit or wider master/slave dual-port static RAM. An M/S　pin is　provided for implementing 16/18-bit or wider memory　applications without the need for separate master and slave　devices or additional discrete logic. Application areas include　interprocessor/multiprocessor designs, communications status　buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),　read or write enable (R/W), and output enable (OE). Two flags are　provided on each port (BUSY and INT). BUSY signals that the port is　trying to access the same location currently being accessed by the　other port. The interrupt flag (INT) permits communication between　ports or systems by means of a mail box. The semaphores are used　to pass a flag, or token, from one port to the other to indicate that a　shared resource is in use. The semaphore logic is comprised of eight　shared latches.　Only one side can control the latch (semaphore) at　any time. Control of a semaphore indicates that a shared resource is　in use. An automatic power-down feature is controlled independently　on each port by a chip enable (CE) pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.

CY7C138 Maximum Ratings

(Above which the useful life may be impaired. For user guidelines,　not tested.)
Storage Temperature .............................. .. ..... –65°C to +150°C
Ambient Temperature with
Power Applied........................................... ..... . –55°C to +125°C
Supply Voltage to Ground Potential ............ .. ..–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................................... ..... –0.5V to +7.0V
DC Input Voltage[5]....................................... ... –0.5V to +7.0V
Output Current into Outputs (LOW)............. ..... 20 mA
Static Discharge Voltage .............................. ..... >2001V
(per MIL–STD–883, Method 3015)
Latch–Up Current ............................................... >200 mA

CY7C138 Features

• True Dual-Ported memory cells which allow　simultaneous reads of the same memory location
• 4K x 8 organization (CY7C138)
• 4K x 9 organization (CY7C139)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 32/36 bits or more using　Master/Slave chip select when using more than one　device
• On-chip arbitration logic
• Semaphores included to permit software handshaking　between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC　

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CY7C137-45PC, CY7C138, CY7C1380

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CY7C137-45PC, CY7C138, CY7C1380 Datasheet PDF download

Part Number: CY7C137-45PC

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