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DDR266, DDR-266, DDR32M8

DDR266, DDR-266, DDR32M8 Selling Leads, Datasheet

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DDR266, DDR-266, DDR32M8 Datasheet download

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Part Number: DDR266

 

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Package Cooled: N/A

D/C: 09+

 

 

 
 
 
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  • DDR 128MX4 PC333

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About DDR110-27T7RL

PDF/DataSheet Download

Datasheet: DDR110-27T7RL

File Size: 50841 KB

Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Download : Click here to Download

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  • DDR-266

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  • DDR 128MX4 PC333

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  • DDR 16MX16 PC400

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  • DDR 16MX16 PC400 PB FREE

  • D/C: 01+& Qty: 3 days  Adddate: 2024-05-14
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About DDR110-27T7RL

PDF/DataSheet Download

Datasheet: DDR110-27T7RL

File Size: 50841 KB

Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Download : Click here to Download

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DDR32M8 Suppliers

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  • DDR 128MX4 PC333

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  • DDR 16MX16 PC333

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  • DDR 16MX16 PC400

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  • DDR 16MX16 PC400 PB FREE

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About DDR110-27T7RL

PDF/DataSheet Download

Datasheet: DDR110-27T7RL

File Size: 50841 KB

Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Download : Click here to Download

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DDR266 General Description

The K4H510838D / K4H511638D is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x 8,388,608 words by 8/16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies,

programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

DDR266 Maximum Ratings

Parameter

Symbol

Value

Unit

Voltage on any pin relative to VSS

VIN, VOUT

-0.5 ~ 3.6

V

Voltage on VDD & VDDQ supply relative to VSS

VDD, VDDQ

-1.0 ~ 3.6

V

Storage temperature

TSTG

-55 ~ +150

°C

Power dissipation

PD

1.5

W

Short circuit current

IOS

50

mA

DDR266 Features

• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
  -. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
  -. Burst length (2, 4, 8)
  -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
• RoHS compliant

DDR266 Connection Diagram

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