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DS90CF388A, DS90CF388AV, DS90CF388AVJD - 228 NSC 2003 -

Table of contents:
Info of DS90CF388A
Info of DS90CF388AV
Info of DS90CF388AVJD - 228 NSC 2003 -

DS90CF388A, DS90CF388AV, DS90CF388AVJD - 228 NSC 2003 - Selling Leads, Datasheet

MFG:NS Package Cooled:QFP D/C:0447+

DS90CF388A, DS90CF388AV, DS90CF388AVJD - 228 NSC 2003 - Picture

DS90CF388A, DS90CF388AV, DS90CF388AVJD - 228 NSC 2003 - Datasheet download

Five Points

Part Number: DS90CF388A

MFG: NS

Package Cooled: QFP

D/C: 0447+

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DS90CF388A General Description

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second).

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet.

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CF388AVJD	.35	0	18700	0	0	1290000	3	366041022
DS90CF388AVJDX	.35	0	18700	0	0	1290000	3	366041022

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

Title	Size in Kbytes	Date
Evaluation Kit for +3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA			View

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes

Title	Size in Kbytes	Date
AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link	25 Kbytes	4-Oct-04	Download
AN-1163: Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map	13 Kbytes	15-May-04	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

DS90CF388A Maximum Ratings

Function	Receiver
Color Depth	24 bpp
Pixel Clock Max	112 MHz
Pixel Clock Min	32.5 MHz
Output Compatibility	LVCMOS
Total Throughput	6272 Mbps
Payload/Channel	784 Mbps
Supply Voltage	3.3 Volt
Temperature Min	-10 deg C
Temperature Max	70 deg C
DisplayType	FPD
Sensing & Imaging	Yes
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