Symbol	Description	Value	Unit
V_CC	Voltage on VDD Pins	-0.5 to 4.6	V
V_DDQ	Voltage in VDDQ Pins	-0.5 to V_DD	V
V_CK	Voltage on Clock Input Pin	-0.5 to 6	V
V_I/O	Voltage on I/O Pins	-0.5 to V_DDQ+0.5 (≤ 4.6 V max.)	V
V_IN	Voltage on Other Input Pins	-0.5 to V_DD+0.5 (≤ 4.6 V max.)	V
I_IN	Input Current on Any Pin	+/- 20	mA
I_OUT	Output Current on Any I/O Pin	+/- 20	mA
P_D	Package Power Dissipation	1.5	W
T_STG	Storage Temperature	-55 to 125	℃
T_BIAS	Temperature Under Bias	-55 to 125	℃

Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation
should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the
Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

GS820E32T-5 Features

•FT pin for user configurable flow through or pipelined operation.
• Dual Cycle Deselect (DCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or QFP package.

GS820E32T-5 Typical Application

The GS820E32 is a 2,097,152 bit high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support.

GS820E32T-5 Connection Diagram

Quick search: A B C D E F G H I J K L M N O P Q R S T U V W X Y 0 1 2 3 4 5 6 7 8 9

GS8208-11E, GS8208-15C, GS820E32T-5

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