GS880Z18AT-166, GS880Z18BT-200, GS880Z36AT-250 Selling Leads, Datasheet
MFG:GSI Package Cooled:TSOP D/C:05+
GS880Z18AT-166, GS880Z18BT-200, GS880Z36AT-250 Datasheet download
Part Number: GS880Z18AT-166
MFG: GSI
Package Cooled: TSOP
D/C: 05+
GS880Z18AT-166, GS880Z18BT-200, GS880Z36AT-250
- Table of contents:
Info of GS880Z18AT-166
Info of GS880Z18BT-200
Info of GS880Z36AT-250
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About GS880Z18AT-166
PDF/DataSheet Download
Datasheet: GS880Z18AT-166
File Size: 771819 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About GS809C
PDF/DataSheet Download
Datasheet: GS809C
File Size: 46098 KB
Manufacturer: VISAY [Vishay Siliconix]
Download : Click here to Download
About GS880Z36AT-250
PDF/DataSheet Download
Datasheet: GS880Z36AT-250
File Size: 771819 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
GS880Z36AT-250 General Description
The GS880Z18/36AT is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO ) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
The GS880Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.
GS880Z36AT-250 Maximum Ratings
| Symbol | Description | Value | Unit |
| VDD | Voltage on VDD Pins | 0.5 to 4.6 | V |
| VDDQ | Voltage in VDDQ Pins | 0.5 to 4.6 | V |
| VCK | Voltage on Clock Input Pin | 0.5 to 6 | V |
| VI/O | Voltage on I/O Pins | 0.5 to VDDQ+0.5 ( 4.6 V max.) |
V |
| VIN | Voltage on Other Input Pins | 0.5 to VDD +0.5 ( 4.6 V max.) |
V |
| IIN | Input Current on Any Pin | +/20 | mA |
| IOUT | Output Current on Any I/O Pin | +/20 | mA |
| PD | Package Power Dissipation | 1.5 | W |
| TSTG | Storage Temperature | 55 to 125 | |
| TBIAS | Temperature Under Bias | 55 to 125 |
GS880Z36AT-250 Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM(TM), NoBL(TM) and
ZBT(TM) SRAMs
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM(TM), NoBL(TM) and
ZBT(TM) SRAMs
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
GS880Z36AT-250 Connection Diagram
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