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HD74ALVC162834ATE, HD74ALVC162835A, HD74ALVC162835AT

Table of contents:
Info of HD74ALVC162834ATE
Info of HD74ALVC162835A
Info of HD74ALVC162835AT

HD74ALVC162834ATE, HD74ALVC162835A, HD74ALVC162835AT Selling Leads, Datasheet

MFG:HITACHI Package Cooled:09+ D/C:1000

HD74ALVC162834ATE, HD74ALVC162835A, HD74ALVC162835AT Picture

HD74ALVC162834ATE, HD74ALVC162835A, HD74ALVC162835AT Datasheet download

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Part Number: HD74ALVC162834ATE

MFG: HITACHI

Package Cooled: 09+

D/C: 1000

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HD74ALVC162835A General Description

The HD74ALVC162835A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V_CC operation.

Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state.

To ensure the high impedance state during power up or power down, OE should be tied to V_CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver.

All outputs, which are designed to sink up to 12 mA, include series dumping resistors to reduce overshoot and undershoot.

HD74ALVC162835A Maximum Ratings

Item	Symbol	Ratings	Unit	Conditions
Supply voltage	V_CC	0.5 to 4.6	V
Input voltage *¹	V_I	0.5 to 4.6	V
Output voltage *^{1, 2}	V_O	0.5 to V_CC +0.5	V	Output : H or L
Input clamp current	I_IK	-50	mA	V_I<0
Output clamp current	I_OK	±50	mA	V_O<0 or V_O >V_CC
Continuous output current	I_O	±50	mA	V_O = 0 to V_CC
VCC, GND current / pin	I_CC or IGND	±100	mA
Maximum power dissipation at Ta = 55°C (in still air)*³	P_T	1	W	TSSOP
Storage temperature	Tstg	65 to 150	°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating condition" is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed.
3. The maximum power dissipation is calculated using a junction temperature of 150°C and board trace length of 750 mils.

HD74ALVC162835A Features

` Supports PC133 and meets "PC SDRAM registered DIMM specification, Rev. 1.1"
` V_CC= 2.3 V to 3.6 V
` Typical VOL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
` Typical VOH undershoot > 2.0 V (@V_CC= 3.3 V, Ta = 25°C)
` High output current ±12 mA (@V_CC = 3.0 V)
` All outputs have series dumping resistors, so no external resistors are required
` t_pd (CLK to Y) = 3.5 ns (Max) (@V_CC = 3.3±0.3 V, C_L = 50 pF, Ta = 0 to 85°C)
` t_pd(CLK to Y) = 2.5 ns (Max) (@V_CC = 3.3±0.3 V, C_L = 30 pF, Ta = 0 to 85°C)

HD74ALVC162835A Connection Diagram

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