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HD74ALVCH16260TELL, HD74ALVCH16270, HD74ALVCH162721

Table of contents:
Info of HD74ALVCH16260TELL
Info of HD74ALVCH16270
Info of HD74ALVCH162721

HD74ALVCH16260TELL, HD74ALVCH16270, HD74ALVCH162721 Selling Leads, Datasheet

MFG:TI Package Cooled:TSSOP D/C:98

HD74ALVCH16260TELL, HD74ALVCH16270, HD74ALVCH162721 Picture

HD74ALVCH16260TELL, HD74ALVCH16270, HD74ALVCH162721 Datasheet download

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Part Number: HD74ALVCH16260TELL

MFG: TI

Package Cooled: TSSOP

D/C: 98

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HD74ALVCH16270 General Description

The HD74ALVCH16270 is used in applications where data must be transferred from a narrow high speed bus to a wide lower frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low to high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path, with a single storage register in the A to 2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active low output enables (OEA, OEB). The control terminals are registered to synchronize the bus direction changes with CLK. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

HD74ALVCH16270 Maximum Ratings

Item	Symbol	Ratings	Unit	Conditions
Supply voltage	V_CC	0.5 to 4.6	V
Input voltage *1,2	V_I	0.5 to 4.6	V	Except I/O ports
Input voltage *1,2	V_I	0.5 to V_CC +0.5	V	I/O ports
Output voltage *1,2	V_O	0.5 to V_CC +0.5	V
Input clamp current	I_IK	-50	mA	V_I < 0
Output clamp current	I_OK	±50	mA	V_O<0 or V_O>V_CC
Continuous output current	I_O	±50	mA	V_O = 0 to V_CC
Continuous output current	I_O	±100	mA
Maximum power dissipation at Ta = 55°C (in still air)*3	P_T	1	W	TSSOP
Storage temperature	Tstg	65 to 150	°C

Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

HD74ALVCH16270 Features

· V_CC= 2.3 V to 3.6 V
· Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
· Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
· High output current ±24 mA (@V_CC = 3.0 V)
· Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

HD74ALVCH16270 Connection Diagram

HD74ALVCH162721 General Description

The HD74ALVCH162721's twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.

The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 W resistors to reduce overshoot and undershoot.

HD74ALVCH162721 Maximum Ratings

Item	Symbol	Ratings	Unit	Conditions
Supply voltage range	V_CC	-0.5 to 4.6	V
Input voltage range ^*1	V_I	-0.5 to 4.6	V
Output voltage range ^{*1, 2}	V_O	-0.5 to V_CC+0.5	V	Output : H or L
Output voltage range ^{*1, 2}	V_O	-0.5 to 4.6	V	V_CC : OFF
Input clamp current	I_IK	-50	mA	V_I < 0
Output clamp current	I_OK	±50	mA	V_O < 0 or V_O > V_CC
Continuous output current	I_O	±50	mA	V_O = 0 to V_CC
Continuous current through V_CC or GND	I_CC or I_GND	±100	mA
Maximum power dissipation at Ta = 25°C (in still air) ^*3	P_T	1	W	TSSOP
Storage temperature	T_stg	-65 to 150	°C

HD74ALVCH162721 Features

· VCC = 2.3 V to 3.6 V
· Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
· Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
· High output current ±12 mA (@VCC = 3.0 V)
· Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
· All outputs have equivalent 26 W series resistors, so no external resistors are required.

HD74ALVCH162721 Connection Diagram

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