MFG:AVAGO/Agilent Package Cooled:Original Package D/C:00+
HDMP-1685, HDMP1685A, HDMP-1685A Datasheet download
MFG: AVAGO/Agilent
Package Cooled: Original Package
D/C: 00+
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PDF/DataSheet Download
Datasheet: HDM08216L-3
File Size: 27965 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: HDM08216L-3
File Size: 27965 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: HDM08216L-3
File Size: 27965 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
This data sheet describes HDMP- 1685A, a 1.25 Gbps, four-channel, 5-pin per channel parallel interface SERDES device. The HDMP-1685A 5-pin parallel interface device enables a single ASIC to drive twice as many channels using half as many parallel lines. This is accomplished without increasing the clock frequency by utilizing the bandwidth on the parallel interface more efficiently.
The HDMP-1685A SERDES is a single silicon bipolar integrated circuit packaged in a 208-pin BGA. This integrated circuit provides a low-cost, small-form-factor physicallayer solution for multi-link 1.25 Gbps cables or optical transceivers. Each IC contains transmit and receive channel circuitry for all four channels.
A 125 MHz LVTTL reference clock must be supplied to the reference clock input pin, RFCT. The transmitter section accepts four, 5-bit-wide parallel SSTL_2 data (TX [0:3] [0:4]), a 125 MHz SSTL_2 byte clock (TC) and serializes them into four high-speed serial streams. The parallel data is expected to be "8B/10B" encoded data, or equivalent. TX and TC are source synchronous. New data are accepted on both edges of TC; this is called Double Data Rate (DDR). HDMP-1685A finds a sampling window in between the two edges of TC to latch TX [0:3] [0:4] data into the input register of the transmitter section.
This timing scheme assumes that the driving ASIC and HDMP-1685A operate in the same clock domain. 8B/10B encoded data comes in 10-bit characters. This data is latched onto the 5 TX pins of each channel in 5-bit groups. It is expected that the beginning half of each 10-bit character is latched on the rising edge of TC.
The transmitter section's PLL locks to the 125 MHz TC. This clock is then multiplied by 10 to generate the 1250 MHz serial clock for the high-speed serial outputs. The high-speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission.
The receiver section accepts four serial electrical data streams at 1250 MBd and recovers the respective original 10-bit-wide data for each channel over a 5-pin parallel interface. The receiver PLL locks onto the incoming serial signal and recovers the high-speed serial clock and data. The serial data is converted back into 10-bit parallel data, optionally recognizing the 8B/10B comma character to establish byte alignment. If comma character detection is enabled by raising the SYNC signal high, the receiver section is able to detect comma characters and indicate their presence on each channel with the appropriate SYN [0:3] signal(s).
The recovered parallel data are presented at SSTL_2-compatible outputs RX [0:3] [0:4], and a pair of 125 MHz SSTL_2 clocks, RC [0:3] [1], and RC [0:3] [0], that are 180 degrees out of phase from one another and which represent the remote clock for that channel. Rising edges of RC [0:3] [1] and RC [0:3] [0] may be used to latch RX data at the destination. Alternatively, both edges of either RC [0:3] [1] or RC [0:3] [0] may be used to latch RX data (DDR). When SYNC is high, the beginning half of the comma character shows up at the rising edge of RC [0:3] [1].
The timing of transmit and receive parallel data with respect to TC and RC [0:3] [0:1] is arranged so that the upstream protocol device can generate and latch data very simply. Specifically, in the TX direction, the ASIC drives four sets of 5-pin TX lines and the TC line with the same timing. The TC line is similar to a 6th data line that is always toggling to provide timing information to the SERDES. On the RX side, the SERDES drives four sets of 5-pin RX data centered between the edges of RC [0:3] [1] or RC [0:3] [0].
For test purposes, the transceiver provides for on-chip parallel loopback functionality controlled through an input pin. Additionally, the byte-edge alignment feature via detection of the positive comma (K28.5+) character may be disabled. This may be useful in proprietary applications that use alternative methods to align the parallel data.
| Symbol | Parameter | Units | Min. | Max. |
| VCC | Supply Voltage | V | 0.5 | 5.0 |
| VIN,LVTTL | RFCT LVTTL Input Voltage | V | 0.7 | VCC + 2.8 |
| VIN,SSTL | SSTL Input Voltage | V | 0.7 | VCC + 0.7 |
| VIN,HS_IN | HS_IN Input Voltage (Differential) | V | 2.2 | |
| Tstg | Storage Temperature | 65 | +150 | |
| Tj | Junction Temperature | 0 | +125 | |
| TC | Case Temperature | 0 | 95 |
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