HDMP-71636A, HDMP8117CN, HDMP-T1636A Selling Leads, Datasheet
MFG:277 Package Cooled:TQFP1010-64 D/C:05+
HDMP-71636A, HDMP8117CN, HDMP-T1636A Datasheet download
Part Number: HDMP-71636A
MFG: 277
Package Cooled: TQFP1010-64
D/C: 05+
HDMP-71636A, HDMP8117CN, HDMP-T1636A
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Info of HDMP-71636A
Info of HDMP8117CN
Info of HDMP-T1636A
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About HDM08216L-3
PDF/DataSheet Download
Datasheet: HDM08216L-3
File Size: 27965 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About HDM08216L-3
PDF/DataSheet Download
Datasheet: HDM08216L-3
File Size: 27965 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About HDMP-T1636A
PDF/DataSheet Download
Datasheet: HDMP-T1636A
File Size: 288400 KB
Manufacturer: HP [Agilent(Hewlett-Packard)]
Download : Click here to Download
HDMP-T1636A General Description
The HDMP-1636A/46A/T1636A transceiver is a single integrated circuit packaged in a plastic QFP package. It provides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet, 1062.5 MBd Fibre Channel, and proprietary link interfaces. It provides complete Serialize/ Deserialize (SerDes) for copper transmission, incorporating the Gigabit Ethernet/Fibre Channel transmit and receive functions into a single device.
This chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power and cost. It is compatible with the IEEE 802.3z specification.
The transmitter section accepts 10-bit wide parallel TTL data and serializes this data into a high speed serial data stream. The parallel data is expected to be "8B/10B" encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the reference clock (used as the transmit byte clock). A 1062.5 MHz reference clock is used in Fibre Channel operation, whereas a 125 MHz reference clock is used in Gigabit Ethernet operation.
The transmitter section's PLL locks to the user supplied reference byte clock. This clock is then multiplied by 10 to generate the high speed serial clock used to generate the high speed output. The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission.
The receiver section accepts a serial electrical data stream at 1062.5 MBd or 1250 MBd and recovers the original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data. The serial data is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment.
This chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power and cost. It is compatible with the IEEE 802.3z specification.
The transmitter section accepts 10-bit wide parallel TTL data and serializes this data into a high speed serial data stream. The parallel data is expected to be "8B/10B" encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the reference clock (used as the transmit byte clock). A 1062.5 MHz reference clock is used in Fibre Channel operation, whereas a 125 MHz reference clock is used in Gigabit Ethernet operation.
The transmitter section's PLL locks to the user supplied reference byte clock. This clock is then multiplied by 10 to generate the high speed serial clock used to generate the high speed output. The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission.
The receiver section accepts a serial electrical data stream at 1062.5 MBd or 1250 MBd and recovers the original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data. The serial data is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment.
HDMP-T1636A Maximum Ratings
| Symbol | Parameter | Units | Min. | Max. |
| VCC | Supply Voltage | V | -0.5 | 5.0 |
| VIN,TTL | TTL Input Voltage | V | -0.7 | VCC +2.8 |
| VIN,HS_IN | HS_IN Input Voltage | V | VCC | |
| IO,TTL | TTL Output Source Current | mA | 13 | |
| Tstg | Storage Temperature | °C | 65 | +150 |
| Tj | Junction Operating Temperature | °C | 0 | +150 |
HDMP-T1636A Features
• IEEE 802.3z Gigabit Ethernet Compatible
• ANSI x3.230-1994 Fibre Channel Compatible (FC-O)
• Supports Serial Data Rates of 1062.5 MBd (Fibre Channel) & 1250 MBd (Gigabit Ethernet)
• Low Power Consumption, 630 mW Typical
• Transmitter and Receiver Functions Incorporated onto a Single IC
• Three Package Sizes Available:
10 mm TQFP (HDMP-T1636A)
10 mm PQFP (HDMP-1636A)
14 mm PQFP (HDMP-1646A)
• 10-Bit Wide Parallel TTL Compatible I/Os
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 kV ESD Protection on All Pins
• ANSI x3.230-1994 Fibre Channel Compatible (FC-O)
• Supports Serial Data Rates of 1062.5 MBd (Fibre Channel) & 1250 MBd (Gigabit Ethernet)
• Low Power Consumption, 630 mW Typical
• Transmitter and Receiver Functions Incorporated onto a Single IC
• Three Package Sizes Available:
10 mm TQFP (HDMP-T1636A)
10 mm PQFP (HDMP-1636A)
14 mm PQFP (HDMP-1646A)
• 10-Bit Wide Parallel TTL Compatible I/Os
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 kV ESD Protection on All Pins
HDMP-T1636A Typical Application
• 1250 MBd Gigabit Ethernet Interface
• 1062.5 MBd Fibre Channel Interface
• Mass Storage System I/O Channel
• Work Station/Server I/O Channel
• Backplane Serialization
• FC Interface for Disk Drives and Arrays
• 1062.5 MBd Fibre Channel Interface
• Mass Storage System I/O Channel
• Work Station/Server I/O Channel
• Backplane Serialization
• FC Interface for Disk Drives and Arrays
HDMP-T1636A Connection Diagram
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