HDMP1012, HDMP-1012, HDMP-1014 Selling Leads, Datasheet
MFG:HP Package Cooled:QFP D/C:96+
HDMP1012, HDMP-1012, HDMP-1014 Datasheet download
Part Number: HDMP1012
MFG: HP
Package Cooled: QFP
D/C: 96+
HDMP1012, HDMP-1012, HDMP-1014
- Table of contents:
Info of HDMP1012
Info of HDMP-1012
Info of HDMP-1014
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About HDM08216L-3
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Datasheet: HDM08216L-3
File Size: 27965 KB
Manufacturer: ETC [ETC]
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About HDMP-1012
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Datasheet: HDMP-1012
File Size: 328890 KB
Manufacturer: HP [Agilent(Hewlett-Packard)]
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About HDMP-1014
PDF/DataSheet Download
Datasheet: HDMP-1014
File Size: 328890 KB
Manufacturer: HP [Agilent(Hewlett-Packard)]
Download : Click here to Download
HDMP-1012 General Description
The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communication.
The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user's viewpoint, these products can be thought of as providing a "virtual ribbon cable" interface for the transmission of data. Parallel data loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link.
The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phaselocked- loop clock extraction circuit also transparently provides for frame synchronization - the user is not troubled with the periodic insertion of frame synchronization words. In addition, the dc balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction.
The Rx chip also includes a state-machine controller (SMC) that provides a startup handshake protocol for the duplex link configuration. The serial data rate of the T/R link is selectable in four ranges (see tables on page 5), and extends from 120 Mbits/s up to 1.25 Gbits/s. The parallel data interface is 16 or 20 bit single-ended ECL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user's control.
The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection. The serial link is synchronous, and both frame synchronization and bit synchronization are maintained. When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup.
User control space is also supported. If Control Available is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available line will indicate the data as a Control Word.
It is the intention of this data sheet to provide the design engineer all of the information regarding the HDMP-1012/1014 chipset necessary to design this product into their application. To assist you in using this data sheet, the following Table of Contents is provided.
The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user's viewpoint, these products can be thought of as providing a "virtual ribbon cable" interface for the transmission of data. Parallel data loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link.
The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phaselocked- loop clock extraction circuit also transparently provides for frame synchronization - the user is not troubled with the periodic insertion of frame synchronization words. In addition, the dc balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction.
The Rx chip also includes a state-machine controller (SMC) that provides a startup handshake protocol for the duplex link configuration. The serial data rate of the T/R link is selectable in four ranges (see tables on page 5), and extends from 120 Mbits/s up to 1.25 Gbits/s. The parallel data interface is 16 or 20 bit single-ended ECL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user's control.
The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection. The serial link is synchronous, and both frame synchronization and bit synchronization are maintained. When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup.
User control space is also supported. If Control Available is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available line will indicate the data as a Control Word.
It is the intention of this data sheet to provide the design engineer all of the information regarding the HDMP-1012/1014 chipset necessary to design this product into their application. To assist you in using this data sheet, the following Table of Contents is provided.
HDMP-1012 Maximum Ratings
| Symbol | Parameter | Units | Min. | Max. |
| VEE | Supply Voltage | V | -7 | +0.5 |
| VIN,ECL | ECL Input Voltage | V | -3 | +0.5 |
| VIN,BLL | H50 Input Voltage | V | -2 | +1 |
| IO,ECL | ECL Output Source Current | mA | +50 | |
| Tstg | Storage Temperature | °C | -40 | +130 |
| TJ | Junction Temperature | °C | -40 | +130 |
| Tmax | Maximum Assembly Temperature (for 10 seconds maximum) | °C | +260 |
HDMP-1012 Features
• Transparent, Extended Ribbon Cable Replacement
• Implemented in a Low Cost Aluminum M-Quad 80 Package
• High-Speed Serial Rate 150-1500 MBaud
• Standard 100K ECL Interface 16, 17, 20, or 21 Bits Wide
• Reliable Monolithic Silicon Bipolar Implementation
• On-chip Phase-Locked Loops
- Transmit Clock Generation
- Receive Clock Extraction
• Implemented in a Low Cost Aluminum M-Quad 80 Package
• High-Speed Serial Rate 150-1500 MBaud
• Standard 100K ECL Interface 16, 17, 20, or 21 Bits Wide
• Reliable Monolithic Silicon Bipolar Implementation
• On-chip Phase-Locked Loops
- Transmit Clock Generation
- Receive Clock Extraction
HDMP-1012 Typical Application
• Backplane/Bus Extender
• Video, Image Acquisition
• Point to Point Data Links
• Implement SCI-FI Standard
• Implement Serial HIPPI Specification
• Video, Image Acquisition
• Point to Point Data Links
• Implement SCI-FI Standard
• Implement Serial HIPPI Specification
HDMP-1012 Connection Diagram
HDMP-1014 General Description
The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communication.
The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user's viewpoint, these products can be thought of as providing a "virtual ribbon cable" interface for the transmission of data. Parallel data loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link.
The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phaselocked- loop clock extraction circuit also transparently provides for frame synchronization - the user is not troubled with the periodic insertion of frame synchronization words. In addition, the dc balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction.
The Rx chip also includes a state-machine controller (SMC) that provides a startup handshake protocol for the duplex link configuration. The serial data rate of the T/R link is selectable in four ranges (see tables on page 5), and extends from 120 Mbits/s up to 1.25 Gbits/s. The parallel data interface is 16 or 20 bit single-ended ECL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user's control.
The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection. The serial link is synchronous, and both frame synchronization and bit synchronization are maintained. When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup.
User control space is also supported. If Control Available is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available line will indicate the data as a Control Word.
It is the intention of this data sheet to provide the design engineer all of the information regarding the HDMP-1012/1014 chipset necessary to design this product into their application. To assist you in using this data sheet, the following Table of Contents is provided.
The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user's viewpoint, these products can be thought of as providing a "virtual ribbon cable" interface for the transmission of data. Parallel data loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link.
The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phaselocked- loop clock extraction circuit also transparently provides for frame synchronization - the user is not troubled with the periodic insertion of frame synchronization words. In addition, the dc balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction.
The Rx chip also includes a state-machine controller (SMC) that provides a startup handshake protocol for the duplex link configuration. The serial data rate of the T/R link is selectable in four ranges (see tables on page 5), and extends from 120 Mbits/s up to 1.25 Gbits/s. The parallel data interface is 16 or 20 bit single-ended ECL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user's control.
The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection. The serial link is synchronous, and both frame synchronization and bit synchronization are maintained. When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup.
User control space is also supported. If Control Available is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available line will indicate the data as a Control Word.
It is the intention of this data sheet to provide the design engineer all of the information regarding the HDMP-1012/1014 chipset necessary to design this product into their application. To assist you in using this data sheet, the following Table of Contents is provided.
HDMP-1014 Maximum Ratings
| Symbol | Parameter | Units | Min. | Max. |
| VEE | Supply Voltage | V | -7 | +0.5 |
| VIN,ECL | ECL Input Voltage | V | -3 | +0.5 |
| VIN,BLL | H50 Input Voltage | V | -2 | +1 |
| IO,ECL | ECL Output Source Current | mA | +50 | |
| Tstg | Storage Temperature | °C | -40 | +130 |
| TJ | Junction Temperature | °C | -40 | +130 |
| Tmax | Maximum Assembly Temperature (for 10 seconds maximum) | °C | +260 |
HDMP-1014 Features
• Transparent, Extended Ribbon Cable Replacement
• Implemented in a Low Cost Aluminum M-Quad 80 Package
• High-Speed Serial Rate 150-1500 MBaud
• Standard 100K ECL Interface 16, 17, 20, or 21 Bits Wide
• Reliable Monolithic Silicon Bipolar Implementation
• On-chip Phase-Locked Loops
- Transmit Clock Generation
- Receive Clock Extraction
• Implemented in a Low Cost Aluminum M-Quad 80 Package
• High-Speed Serial Rate 150-1500 MBaud
• Standard 100K ECL Interface 16, 17, 20, or 21 Bits Wide
• Reliable Monolithic Silicon Bipolar Implementation
• On-chip Phase-Locked Loops
- Transmit Clock Generation
- Receive Clock Extraction
HDMP-1014 Typical Application
• Backplane/Bus Extender
• Video, Image Acquisition
• Point to Point Data Links
• Implement SCI-FI Standard
• Implement Serial HIPPI Specification
• Video, Image Acquisition
• Point to Point Data Links
• Implement SCI-FI Standard
• Implement Serial HIPPI Specification
HDMP-1014 Connection Diagram
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