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HYB18T256400AFL-3.7, HYB18T256400BF2.5, HYB18T256400BF-25F

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Info of HYB18T256400AFL-3.7
Info of HYB18T256400BF2.5
Info of HYB18T256400BF-25F

HYB18T256400AFL-3.7, HYB18T256400BF2.5, HYB18T256400BF-25F Selling Leads, Datasheet

MFG:INFINEON Package Cooled:FBGA60 D/C:07+

HYB18T256400AFL-3.7, HYB18T256400BF2.5, HYB18T256400BF-25F Picture

HYB18T256400AFL-3.7, HYB18T256400BF2.5, HYB18T256400BF-25F Datasheet download

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Part Number: HYB18T256400AFL-3.7

MFG: INFINEON

Package Cooled: FBGA60

D/C: 07+

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HYB18T256400BF-25F General Description

The 256-Mbit Double-Data-Rate-Two SDRAM is a highspeed CMOS Synchronous DRAM device containing 268,435,456 bits and internally configured as a quad-bank DRAM. The device is organized as either 16 Mbit × 4 I/O × 4 banks, 8 Mbit × 8 I/O × 4 banks or 4 Mbit ×16 I/O × 4 banks chip. These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 for performance figures.

The device is designed to comply with all DDR2 DRAM key features:
• Posted CAS with additive latency,
• Write latency = read latency - 1,
• Normal and weak strength data-output driver,
• Off-Chip Driver (OCD) impedance adjustment
• On-Die Termination (ODT) function.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

A is used to convey row, column and bank address information in a RAS-CAS multiplexing style.

The DDR2 device operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.

The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of
operation.

The DDR2 SDRAM is available in P(G)-TFBGA-60 and P(G)- TFBGA-84 packages.

HYB18T256400BF-25F Maximum Ratings

Symbol	Parameter	Rating		Unit	Note
Symbol	Parameter	Min.	Max.	Unit	Note
V_DD	Voltage on V_DD pin relative to V_SS	1.0	+2.3	V	¹⁾
V_DDQ	Voltage on V_DDQ pin relative to V_SS	0.5	+2.3	V	¹⁾²⁾
V_DDL	Voltage on V_DDL pin relative to V_SS	0.5	+2.3	V	¹⁾²⁾
V_IN, V_OUT	Voltage on any pin relative to V_SS	0.5	+2.3	V	¹⁾
T_STG	Storage Temperature	55	+100		¹⁾²⁾

1) When V_DDand V_DDQand V_DDLare less than 500 mV; V_REF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

HYB18T256400BF-25F Features

The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• 1.8 V ± 0.1 V Power Supply
   1.8 V ± 0.1 V (SSTL_18) compatible I/O
• DRAM organizations with 4, 8 and 16 data in/outputs
• Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned
   with read data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe operation
• Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power- Down modes
• Average Refresh Period 7.8 s at a TCASE lower than85, 3.9 s between 85 and 95
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
• 1K page size
• Packages: P(G)-TFBGA-60 for *4 & *8 components, P(G)-TFBGA-84 for *16 components
• RoHS Compliant Products1)
• All Speed grades faster than DDR2400 comply with DDR2400 timing specifications when run at a clock
   rate of 200 MHz.

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