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IC61SF51218, IC61SP12832, IC61SP12832-5TQ

Table of contents:
Info of IC61SF51218
Info of IC61SP12832
Info of IC61SP12832-5TQ

IC61SF51218, IC61SP12832, IC61SP12832-5TQ Selling Leads, Datasheet

MFG:ICSI Package Cooled:TQFP D/C:09+

IC61SF51218, IC61SP12832, IC61SP12832-5TQ Picture

IC61SF51218, IC61SP12832, IC61SP12832-5TQ Datasheet download

Five Points

Part Number: IC61SF51218

MFG: ICSI

Package Cooled: TQFP

D/C: 09+

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IC61SP12832 General Description

The ICSI IC61SP12832,IC61SP12836 are high-speed, lowpower synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 131,072 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61SP12832,IC61SP12836 and controlled by theADV (burst address advance) input pin.

The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.

IC61SP12832 Maximum Ratings

Symbol	Parameter	Value	Unit
T_BIAS	Temperature Under Bias	-40 to +85
T_STG	Storage Temperature	-55 to +150
P_D	Power Dissipation	1.6	W
I_OUT	Output Current (per I/O)	100	mA
V_IN, V_OUT	Voltage Relative to GND for I/O Pins	-0.5 to V_CCQ + 0.3	V
V_IN	Voltage Relative to GND for for Address and Control Inputs	-0.5 to V_CC + 0.5	V
V_CC	Voltage on Vcc Supply Relatiive to GND	-0.5 to 4.6	V

IC61SP12832 Features

• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Common data inputs and data outputs
• 100-Pin TQFP (JEDEC LQFP) and 119-pin PBGA package
• Single +3.3V, +10%, 5% power supply
• Power-down snooze mode

IC61SP12832 Connection Diagram

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