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IS61NLF51218A, IS61NLF51218A-7.5TQI, IS61NLF51236

Table of contents:
Info of IS61NLF51218A
Info of IS61NLF51218A-7.5TQI
Info of IS61NLF51236

IS61NLF51218A, IS61NLF51218A-7.5TQI, IS61NLF51236 Selling Leads, Datasheet

MFG:ISSI, Integrated Silicon Solution Inc Category:Integrated Circuits (ICs) Package Cooled:TQFP D/C:09+

IS61NLF51218A, IS61NLF51218A-7.5TQI, IS61NLF51236 Picture

IS61NLF51218A, IS61NLF51218A-7.5TQI, IS61NLF51236 Datasheet download

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Part Number: IS61NLF51218A

Category: Integrated Circuits (ICs)

MFG: ISSI, Integrated Silicon Solution Inc

Package Cooled: TQFP

D/C: 09+

Description: IC SRAM 9MB SYNC 100-TQFP

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IS61NLF51218A General Description

The 9 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated with ISSI's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.

All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.

IS61NLF51218A Maximum Ratings

Symbol	Parameter	Value	Unit
T_STG	Storage Temperature	65 to +150	°C
P_D	Power Dissipation	1.6	W
I_OUT	Output Current (per I/O)	100	mA
V_IN, V_OUT	Voltage Relative to V_SS for I/O Pins	0.5 to V_DDQ + 0.3	V
V_IN	Voltage Relative to V_SS for for Address and Control Inputs	0.3 to 4.6	V

Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IS61NLF51218A Features

• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165- ball PBGA packages
• Power supply: NVF: V_DD 2.5V (± 5%), V_DDQ 2.5V (± 5%) NLF: V_DD 3.3V (± 5%), V_DDQ 3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available

IS61NLF51218A Connection Diagram

IS61NLF51218A-7.5TQI Parameters

Technical/Catalog Information	IS61NLF51218A-7.5TQI
Vendor	ISSI, Integrated Silicon Solution Inc
Category	Integrated Circuits (ICs)
Memory Type	SRAM - Synchronous
Memory Size	9M (512K x 18)
Speed	117MHz
Interface	Parallel
Package / Case	100-TQFP
Packaging	Tray
Voltage - Supply	3.135 V ~ 3.465 V
Operating Temperature	-40°C ~ 85°C
Format - Memory	RAM
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	IS61NLF51218A 7 5TQI IS61NLF51218A75TQI

IS61NLF51236 General Description

The 18 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.

All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.

IS61NLF51236 Maximum Ratings

Symbol	Parameter	Value	Unit
T_STG	Storage Temperature	65 to +150	°C
P_D	Power Dissipation	1.6	W
I_OUT	Output Current (per I/O)	100	mA
V_IN, V_OUT	Voltage Relative to V_SSfor I/O Pins	0.5 to V_DDQ + 0.3	V
V_IN	Voltage Relative to V_SS for for Address and Control Inputs	0.3 to 4.6	V

IS61NLF51236 Features

• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages
• Power supply: NVF: V_DD 2.5V (± 5%), V_DDQ 2.5V (± 5%) NLF: V_DD 3.3V (± 5%), V_DDQ 3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available

IS61NLF51236 Connection Diagram

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