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K4D551638D-LC50, K4D551638D-LC60, K4D551638D-TC

K4D551638D-LC50, K4D551638D-LC60, K4D551638D-TC Selling Leads, Datasheet

MFG:SAMSUNG  Package Cooled:TSOP66  D/C:2005+

K4D551638D-LC50, K4D551638D-LC60, K4D551638D-TC Picture

K4D551638D-LC50, K4D551638D-LC60, K4D551638D-TC Datasheet download

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Part Number: K4D551638D-LC50

 

MFG: SAMSUNG

Package Cooled: TSOP66

D/C: 2005+

 

 

 
 
 
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About K4D261638

PDF/DataSheet Download

Datasheet: K4D261638

File Size: 231302 KB

Manufacturer: SAMSUNG [Samsung semiconductor]

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About K4D261638

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Datasheet: K4D261638

File Size: 231302 KB

Manufacturer: SAMSUNG [Samsung semiconductor]

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About K4D551638D-TC

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Datasheet: K4D551638D-TC

File Size: 236220 KB

Manufacturer: SAMSUNG [Samsung semiconductor]

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K4D551638D-TC General Description

The K4D551638D is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

K4D551638D-TC Maximum Ratings

Symbol Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V
Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 2.0 W
Short circuit current IOS 50 mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

K4D551638D-TC Features

• 2.6V + 0.1V power supply for device operation
• 2.6V + 0.1V power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 2 DQS's ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle) for -TC2A/33/36/40/45
• 64ms refresh period (8K cycle) for -TC50/60
• 66pin TSOP-II
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin

K4D551638D-TC Connection Diagram

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