MFG:SAMSUNG Package Cooled:BGA D/C:05+
K4D553235F-GC, K4D553235FGC2A, K4D553235F-GC33 2M32B4B F Datasheet download
MFG: SAMSUNG
Package Cooled: BGA
D/C: 05+
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PDF/DataSheet Download
Datasheet: K4D553235F-GC
File Size: 395732 KB
Manufacturer: SAMSUNG [Samsung semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: K4D261638
File Size: 231302 KB
Manufacturer: SAMSUNG [Samsung semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: K4D261638
File Size: 231302 KB
Manufacturer: SAMSUNG [Samsung semiconductor]
Download : Click here to Download
The K4D553235F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
| Parameter | Symbol | Value | Unit |
| Voltage on any pin relative to Vss | VIN, VOUT | -0.5 ~ 3.6 | V |
| Voltage on VDD supply relative to Vss | VDD | -1.0 ~ 3.6 | V |
| Voltage on VDDQ supply relative to Vss | VDDQ | -0.5 ~ 3.6 | V |
| Storage temperature | TSTG | -55 ~ +150 | °C |
| Power dissipation | PD | 2.0 | W |
| Short circuit current | IOS | 50 | mA |
Note :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
• 1.8V ± 0.1V power supply for device operation
• 1.8V ± 0.1V power supply for I/O interface
• SSTL_18 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS's ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 450MHz
• Maximum data rate up to 900Mbps/pin
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