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KM736V689A, KM736V689AT10, KM736V689AT-10

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Info of KM736V689A
Info of KM736V689AT10
Info of KM736V689AT-10

KM736V689A, KM736V689AT10, KM736V689AT-10 Selling Leads, Datasheet

MFG:3266 Package Cooled:QFP D/C:08+

KM736V689A, KM736V689AT10, KM736V689AT-10 Picture

KM736V689A, KM736V689AT10, KM736V689AT-10 Datasheet download

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Part Number: KM736V689A

MFG: 3266

Package Cooled: QFP

D/C: 08+

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KM736V689A General Description

The KM736V689A is a 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

It is organized as 64K words of 36bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status processor(
ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system¢s burst sequence and are controlled by the burst address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(linear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK.

The KM736V689A is fabricated using SAMSUNG¢s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.

KM736V689A Maximum Ratings

PARAMETER	SYMBOL	RATING	UNIT
Voltage on VDD Supply Relative to V_SS	V_DD	-0.3 to 4.6	V
Voltage on VDDQ Supply Relative to V_SS	V_DDQ	V_DD	V
Voltage on Input Pin Relative to V_SS	V_IN	-0.3 to 6.0	V
Voltage on I/O Pin Relative to V_SS	V_IO	-0.3 to V_DDQ+0.5	V
Power Dissipation	P_D	1.2	W
Storage Temperature	T_STG	-65 to 150
Operating Temperature	T_OPR	0 to 70
Storage Temperature Range Under Bias	T_BIAS	-10 to 85

KM736V689A Features

• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear burst.
• Three Chip Enables for simple depth expansion with No Data Contention ; 2 cycle Enable, 1 cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A

KM736V689A Connection Diagram

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