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LAN91C96, LAN91C961, LAN91C96AR64

Table of contents:
Info of LAN91C96
Info of LAN91C961
Info of LAN91C96AR64

LAN91C96, LAN91C961, LAN91C96AR64 Selling Leads, Datasheet

MFG:SMSC Package Cooled:QFP D/C:08+/09+

LAN91C96, LAN91C961, LAN91C96AR64 Picture

LAN91C96, LAN91C961, LAN91C96AR64 Datasheet download

Five Points

Part Number: LAN91C96

MFG: SMSC

Package Cooled: QFP

D/C: 08+/09+

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LAN91C96 General Description

The LAN91C96 is a VLSI Ethernet Controller that combines Local Bus, PCMCIA, and Motorola 68000 bus interfaces in one chip. LAN91C96 integrates all MAC and physical layer functions, as well as the packet RAM, needed to implement a high performance 10BASE-T (twisted pair) node. For 10BASE5 (thick coax), 10BASE2 (thin coax), and 10BASE-F (fiber) implementations, the LAN91C96 interfaces to external transceivers via the provided AUI port. Only one additional IC is required for most applications. The LAN91C96 comes with Full Duplex Switched Ethernet (FDSWE) support allowing the controller to provide much higher throughput. 6K bytes of RAM is provided to support enhanced throughput and compensate for any increased system service latencies. The controller implements multiple advanced power-down modes including Magic Packet to conserve power and operate more efficiently. The LAN91C96 can directly interface with the Local Bus, PCMCIA, and 68000 buses and deliver no-wait-state operation. For Local Bus and PCMCIA interfaces, the LAN91C96 occupies 16 I/0 locations and no memory space except for PCMCIA attribute memory space. The same I/O space is used for both LOCAL BUS and PCMCIA operations. Its shared memory is sequentially accessed with 40ns access times to any of its registers, including its packet memory. DMA services are not used by the LAN91C96, virtually de-coupling network traffic from local or system bus utilization. For packet memory management, the LAN91C96 integrates a unique hardware Memory Management Unit (MMU) with enhanced performance and decreased software overhead when compared to ring buffer and linked list architectures. The LAN91C96 is portable to different CPU and bus platforms due to its flexible bus interface, flat memory structure (no pointers), and its loosely coupled buffered architecture (not sensitive to latency).

The LAN91C96 is available in 100-pin QFP and TQFP (1.0 mm body thickness) packages. The low profile TQFP is ideal for mobile applications such as PC Card LAN adapters. The LAN91C96 operates with a single power supply voltage of 5.0V. Revisions E and later will also operate using a single 3.3V power supply.

LAN91C96 Maximum Ratings

Operating Temperature Range ..........................................0°C to 70°C
Storage Temperature Range ......................................-55°C to +150°C
Lead Temperature Range (soldering, 10 seconds) .....................+325°C
Positive Voltage on any pin, with respect to Ground ..............V_CC + 0.3V
Negative Voltage on any pin, with respect to Ground ..................... -0.3V
Maximum V_CC.................................................................................... +7V
*Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied.

Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

LAN91C96 Features

` Non-PCI Single-Chip Ethernet Controller
` A Subset of Motorola 68000 Bus Interface Support
` Fully Supports Full Duplex Switched Ethernet
` Supports Enhanced Transmit Queue Management
` 6K Bytes of On-Chip RAM
` Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards
` Automatic Detection of TX/RX Polarity Reversal
` Enhanced Power Management Features
` Supports "Magic Packet" Power Management Technology
` Simultasking Early Transmit and Early Receive Functions
` Enhanced Early Transmit Function
` Receive Counter for Enhanced Early Receive
` Hardware Memory Management Unit
` Optional Configuration via Serial EEPROM Interface (Jumperless)
` Supports single +5V or +3.3V (for Revisions E and Later) VCC Designs
` Supports Mixed Voltage External PHY Designs1
` Low Power CMOS Design
` 100 Pin QFP and TQFP (1.0 mm body Thickness) Packages
` Pin Compatible with the LAN91C92 and LAN91C94

LAN91C96 Connection Diagram

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