LC72700 (SMD), LC72700N, LC72706E Selling Leads, Datasheet
MFG:SANYO Package Cooled:SMD D/C:99
LC72700 (SMD), LC72700N, LC72706E Datasheet download
Part Number: LC72700 (SMD)
MFG: SANYO
Package Cooled: SMD
D/C: 99
LC72700 (SMD), LC72700N, LC72706E
- Table of contents:
Info of LC72700 (SMD)
Info of LC72700N
Info of LC72706E
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About LC7.0
PDF/DataSheet Download
Datasheet: LC7.0
File Size: 600987 KB
Manufacturer: MICROSEMI [Microsemi Corporation]
Download : Click here to Download
About LC7.0
PDF/DataSheet Download
Datasheet: LC7.0
File Size: 600987 KB
Manufacturer: MICROSEMI [Microsemi Corporation]
Download : Click here to Download
About LC72706E
PDF/DataSheet Download
Datasheet: LC72706E
File Size: 168175 KB
Manufacturer: SANYO [Sanyo Semicon Device]
Download : Click here to Download
LC72706E General Description
The LC72706E is a data demodulation IC for receiving FM multiplex broadcasts for mobile receivers in the DARC format. In conjunction with a bandpass filter IC (either the LV3400M or the LV3403M), the LC72706E can form a compact yet high-functionality FM multiplex reception system. This IC supports all the FM multiplex frame structures (methods A, B, and C) in the ITU-R recommendations.
LC72706E Maximum Ratings
|
Parameter |
Symbol |
Conditions |
Ratings |
Unit |
| Maximum supply voltage |
VDD max |
0.3 to +7.0 |
V | |
| Input voltage |
VIN 1 |
CE, CL, DI, RST, STNBY |
0.3 to +7.0 |
V |
|
VIN 2 |
Pins other than VIN1 |
0.3 to VDD + 0.3 |
V | |
| Output voltage |
VOUT 1 |
DO |
0.3 to +7.0 |
V |
|
VOUT 2 |
Pins other than VOUT1 |
0.3 to VDD + 0.3 |
V | |
| Output current |
IOUT |
BLOCK, FLOCK, DO |
0 to 4.0 |
mA |
| Allowable power dissipation |
Pd max |
Ta 85°C |
400 |
mW |
| Operating temperature |
Topr |
-40to+85 |
°C | |
| Storage temperature |
Tstg |
-55to+125 |
°C |
LC72706E Features
• MSK delay detection circuit based on a 1T delay
• Error correction function based on a 2T delay (in the MSK detector stage)
• Digital PLL based clock regeneration circuit
• Shift-register type 1T and 2T delay circuits
• Block and frame synchronization detection circuit
• Serial control data transfer based support for the A, B,and C FM multiplex frame structures
• Function for setting the number of allowable BIC errors,the number of synchronization protection.
• Error correction using (272, 190) codes
• Layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for vertical correction
• 7.2-MHz crystal oscillator circuit
• Error correction function based on a 2T delay (in the MSK detector stage)
• Digital PLL based clock regeneration circuit
• Shift-register type 1T and 2T delay circuits
• Block and frame synchronization detection circuit
• Serial control data transfer based support for the A, B,and C FM multiplex frame structures
• Function for setting the number of allowable BIC errors,the number of synchronization protection.
• Error correction using (272, 190) codes
• Layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for vertical correction
• 7.2-MHz crystal oscillator circuit
LC72706E Typical Application
• Receivers for DARC format mobile receiver FM multiplex broadcasts
LC72706E Connection Diagram
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