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LH28F008SCH-V, LH28F008SCH-ZU-120, LH28F008SCN-85

Table of contents:
Info of LH28F008SCH-V
Info of LH28F008SCH-ZU-120
Info of LH28F008SCN-85

LH28F008SCH-V, LH28F008SCH-ZU-120, LH28F008SCN-85 Selling Leads, Datasheet

MFG:SHARP Package Cooled:TSOP40 D/C:N/A

LH28F008SCH-V, LH28F008SCH-ZU-120, LH28F008SCN-85 Picture

LH28F008SCH-V, LH28F008SCH-ZU-120, LH28F008SCN-85 Datasheet download

Five Points

Part Number: LH28F008SCH-V

MFG: SHARP

Package Cooled: TSOP40

D/C: N/A

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LH28F008SCH-V General Description

The LH28F008SC-V/SCH-V flash memories with Smart 5 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SC-V/SCH-V offer three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs.

LH28F008SCH-V Maximum Ratings

Operating Temperature
• LH28F008SC-V
    During Read, Block Erase, Byte Write
    and Lock-Bit Configuration ........... 0 to +70 ^{(NOTE 1)}    Temperature under Bias.........................10 to +80
• LH28F008SCH-V
    During Read, Block Erase, Byte Write
    and Lock-Bit Configuration ... ...25 to +85 ^{(NOTE 2)}    Temperature under Bias............. ...........25 to +85
Storage Temperature.............................. 65 to +125
Voltage On Any Pin
    (except VCC, VPP, and RP#) ...2.0 to +7.0 V ^{(NOTE 3)}VCC Supply Voltage................. ...2.0 to +7.0 V^{(NOTE 3)}VPP Update Voltage during
    Block Erase, Byte Write and
    Lock-Bit Configuration .. ....2.0 to +14.0 V ^{(NOTE 3, 4)}
RP# Voltage with Respect to
    GND during Lock-Bit
    Configuration Operations.. 2.0 to +14.0 V ^{(NOTE 3, 4)}Output Short Circuit Current .............. ....100 mA ^{(NOTE 5)}

LH28F008SCH-V Features

• Smart 5 technology
    5 V V_CC
    5 V or 12 V V_PP
• High performance read access time
LH28F008SC-V85/SCH-V85
    85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)
LH28F008SC-V12/SCH-V12
    120 ns (5.0±0.5 V)
• Enhanced automated suspend options
    Byte write suspend to read
    Block erase suspend to byte write
    Block erase suspend to read
• Enhanced data protection features
    Absolute protection with VPP = GND
    Flexible block locking
    Block erase/byte write lockout during power transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
    Sixteen 64 k-byte erasable blocks
• Enhanced cycling capability
    100 000 block erase cycles
    1.6 million block erase cycles/chip
• Low power management
    Deep power-down mode
    Automatic power saving mode decreases I_CC in static mode
• Automated byte write and block erase
    Command user interface
    Status register
• ETOX^TM* V nonvolatile flash technology
• Packages
    40-pin TSOP Type I (TSOP040-P-1020)
Normal bend/Reverse bend
    44-pin SOP (SOP044-P-0600)
    48-ball CSP (FBGA048-P-0608)

LH28F008SCH-V Connection Diagram

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