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M393T6553CZ3-CCC, M393T6553CZA, M393T6553CZA-CE6

Table of contents:
Info of M393T6553CZ3-CCC
Info of M393T6553CZA
Info of M393T6553CZA-CE6

M393T6553CZ3-CCC, M393T6553CZA, M393T6553CZA-CE6 Selling Leads, Datasheet

MFG:Samsung Orig [64Mx8 9C] D/C:09+

M393T6553CZ3-CCC, M393T6553CZA, M393T6553CZA-CE6 Picture

M393T6553CZ3-CCC, M393T6553CZA, M393T6553CZA-CE6 Datasheet download

Five Points

Part Number: M393T6553CZ3-CCC

MFG: Samsung Orig [64Mx8 9C]

Package Cooled:

D/C: 09+

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M393T6553CZA-CE6 Maximum Ratings

Symbol	Parameter	Rating	Units	Notes
V_DD	Voltage on V_DD pin relative to V_SS	- 1.0 V ~ 2.3 V	V	1
V_DDQ	Voltage on V_DDQ supply relative to Vss	- 0.5 V ~ 2.3 V	V	1
V_DDL	Voltage on V_DDL pin relative to V_SS	- 0.5 V ~ 2.3 V	V	1
V_IN, V_OUT	VOUT Voltage on any pin relative to V_SS	- 0.5 V ~ 2.3 V	V	1
T_STG	Storage Temperature	-55 to +100		1,2

Note :
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

M393T6553CZA-CE6 Features

• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a T_CASE 85°C, 3.9us at 85°C < T_CASE 95 °C
- support High Temperature Self-Refresh rate enable feature
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
• All of Lead-free products are compliant for RoHS

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