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M50FLW040K1, M50FLW080A, M50FLW080AK5G

Table of contents:
Info of M50FLW040K1
Info of M50FLW080A
Info of M50FLW080AK5G

M50FLW040K1, M50FLW080A, M50FLW080AK5G Selling Leads, Datasheet

MFG:ST Package Cooled:PLCC D/C:N/A

M50FLW040K1, M50FLW080A, M50FLW080AK5G Picture

M50FLW040K1, M50FLW080A, M50FLW080AK5G Datasheet download

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Part Number: M50FLW040K1

MFG: ST

Package Cooled: PLCC

D/C: N/A

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M50FLW080A General Description

The M50FLW080 is a 8 Mbit (1M x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing on production lines, an optional 12V power supply can be used to reduce the erasing and programming time.

The memory is divided into 16 Uniform Blocks of 64 KBytes each, three of which are divided into 16 uniform sectors of 4 KBytes each (see APPENDIX A. for details). All blocks and sectors can be erased independently. So, it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental program or erase commands from modifying their contents.

Program and erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set to control the memory is consistent with the JEDEC standards. Two different bus interfaces are supported by the memory:
`The primary interface, the FWH/LPC Interface, uses Intel's proprietary Firmware Hub (FWH) and Low Pin Count (LPC) protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets. The M50FLW080 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.
`The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers, for production line programming prior to fitting the device in a PC Motherboard.

The memory is supplied with all the bits erased (set to '1').

M50FLW080A Maximum Ratings

Symbol	Parameter	Min.	Max.	Unit
T_STG	Storage Temperature	-65	150
T_LEAD	Lead Temperature during Soldering	See note 1
V_IO	Input or Output range²	-0.6	V_CC + 0.6	V
V_CC	Supply Voltage	-0.6	4.0	V
V_PP	Program Voltage	-0.6	13	V
V_ESD	Electrostatic Discharge Voltage (Human Body model) ³	-2000	2000	V

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK^® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. Minimum voltage may undershoot to 2V for less than 20ns during transitions. Maximum voltage may overshoot to V_CC + 2V for less than 20ns during transitions.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )

M50FLW080A Features

` FLASH MEMORY
    Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1) used in PC BIOS applications
    5 Signal Communication Interface supporting Read and Write Operations
    5 Additional General Purpose Inputs for platform design flexibility
    Synchronized with 33MHz PCI clock
` 16 BLOCKS OF 64 KBYTES
    13 blocks of 64 KBytes each
    3 blocks, subdivided into 16 uniform sectors of 4 KBytes each
    Two blocks at the top and one at the bottom (M50FLW080A)
    One block at the top and two at the bottom (M50FLW080B)
` ENHANCED SECURITY
    Hardware Write Protect Pins for Block Protection
    Register-based Read and Write Protection
    Individual Lock Register for Each 4 KByte Sector
` SUPPLY VOLTAGE
    V_CC = 3.0 to 3.6V for Program, Erase and Read Operations
    V_PP = 12V for Fast Program and Erase
` TWO INTERFACES
    Auto Detection of Firmware Hub (FWH) or Low Pin Count (LPC) Memory Cycles for Embedded Operation with PC Chipsets
    Address/Address Multiplexed (A/A Mux)
    Interface for programming equipment compatibility.
` PROGRAMMING TIME: 10s typical
` PROGRAM/ERASE CONTROLLER
    Embedded Program and Erase algorithms
    Status Register Bits
` PROGRAM/ERASE SUSPEND
    Read other Blocks/Sectors during Program Suspend
    Program other Blocks/Sectors during Erase Suspend
` ELECTRONIC SIGNATURE
    Manufacturer Code: 20h
    Device Code (M50FLW080A): 80h
    Device Code (M50FLW080B): 81h

M50FLW080A Connection Diagram

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