M50LPW040, M50LPW040N1, M50LPW080N5 Selling Leads, Datasheet
MFG:ST Package Cooled:PLCC32 D/C:03+
M50LPW040, M50LPW040N1, M50LPW080N5 Datasheet download

Part Number: M50LPW040
MFG: ST
Package Cooled: PLCC32
D/C: 03+
MFG:ST Package Cooled:PLCC32 D/C:03+
M50LPW040, M50LPW040N1, M50LPW080N5 Datasheet download

MFG: ST
Package Cooled: PLCC32
D/C: 03+
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PDF/DataSheet Download
Datasheet: M50LPW040
File Size: 279214 KB
Manufacturer: STMICROELECTRONICS [STMicroelectronics]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: M50LPW040N1T
File Size: 279214 KB
Manufacturer: STMICROELECTRONICS [STMicroelectronics]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: M50LPW080N5
File Size: 656447 KB
Manufacturer: STMICROELECTRONICS [STMicroelectronics]
Download : Click here to Download
The M50LPW040 is a 4 Mbit (512Kb x8) nonvolatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Two different bus interfaces are supported by the memory. The primary interface is the Low Pin Count (or LPC) Standard Interface. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50LPW040 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.
The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.
The memory is offered in TSOP40 (10 x 20mm) and PLCC32 packages and it is supplied with all the bits erased (set to '1').
|
Symbol |
Parameter |
Value |
Unit |
|
TA |
Ambient Operating Temperature (Temperature Range Option 1) | 0 to 70 | |
| Ambient Operating Temperature(Temperature Range Option 5) |
20 to 85 |
||
|
TBIAS |
Temperature Under Bias |
50 to 125 |
|
|
TSTG |
Storage Temperature |
65 to 150 |
V |
|
VIO (2) |
Input or Output Voltage |
0.6 to VCC + 0.6 |
V |
|
VCC |
Supply Voltage |
0.6 to 4 |
V |
|
VPP |
Program Voltage |
0.6 to 13 |
V |

