MFG:Fujitsu Package Cooled:13789+ D/C:1920
MBM29LV160T90PFTN, MBM29LV160TD-90PFTN, MBM29LV160TE Datasheet download
MFG: Fujitsu
Package Cooled: 13789+
D/C: 1920
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PDF/DataSheet Download
Datasheet: MBM100A6
File Size: 79491 KB
Manufacturer: HITACHI [Hitachi Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MBM100A6
File Size: 79491 KB
Manufacturer: HITACHI [Hitachi Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MBM29LV160TE -12
File Size: 907683 KB
Manufacturer: Fujitsu
Download : Click here to Download
The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (I), 48-pin CSOP and 48-ball FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in tandard EPROM programmers.
The standard MBM29LV160TE/BE offers access times of 70 ns, 90 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.
The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the Embedded ProgramTM* Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before xecuting the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
(Continued)
|
Parameter |
Symbol |
Rating |
Unit | |
|
Min. |
Max. | |||
| Storage Temperature |
Tstg |
55 |
+125 |
|
| Ambient Temperature with Power Applied |
TA |
40 |
+85 |
|
| Voltage with Respect to Ground All pins except A9, OE, RESET (Note 1) |
VIN, VOUT |
0.5 |
VCC+0.5 |
V |
| Power Supply Voltage (Note 1) |
VCC |
0.5 |
+5.5 |
V |
| A9 , OE, and RESET (Note 2) |
VIN |
0.5 |
+13.0 |
V |
Notes: 1. Minimum DC voltage on input or l/O pins are 0.5 V. During voltage transitions, inputs may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are VCC +0.5 V.
During voltage transitions,outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE, and RESET pins are 0.5 V. During voltage transitions, A9, OE, and RESET pins may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE, and RESET
pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (VIN VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
` 0.23 m m Process Technology
` Single 3.0 V read, program and erase
Minimizes system level power requirements
` Compatible with JEDEC-standard commands
Uses same software commands as E2 PROMs
` Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)
48-pin CSOP (Package suffix: PCV)
48-ball FBGA (Package suffix: PBT)
` Minimum 100,000 program/erase cycles
` High performance
70 ns maximum access time
` Sector erase architecture
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase
` Boot Code Sector Architecture
T = Top sector
B = Bottom sector
` Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
` Embedded ProgramTM Algorithms
Automatically programs and verifies data at specified address
` Data Polling and Toggle Bit feature for detection of program or erase cycle completion
` Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
` Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
` Low VCC write inhibit 2.5 V
` Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
` Sector protection
Hardware method disables any combination of sectors from program or erase operations
` Sector Protection Set function by Extended sector Protection command
` Fast Programming Function by Extended command
` Temporary sector unprotection
Temporary sector unprotection via the RESET pin
` In accordance with CFI ( Common Flash Memory Interface)
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