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The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller family. As shown in the block diagram, they are composed of: • High performance CPU system - High performance core • Single issue integer core • Compatible with PowerPC instruction set architecture • Precise exception model • Floating point • Extensive system development support - On-chip watchpoints and breakpoints - Program flow tracking - Background debug mode (BDM) - IEEE-ISTO Nexus 5001-1999 Class 3 Debug Interface - MPC500 system interface (USIU, BBC, L2U) - Fully static design - Four major power saving modes • On, doze, sleep, deep-sleep and power-down - 32-Kbyte static RAM (CALRAM) - 512-Kbyte flash (UC3F) on MPC563/MPC564 - General-purpose I/O support • On address (24) and data (32) pins • 16 GPIO in MIOS14 • Many peripheral pins can be used as GPIO when not used as primary functions • 2.6-V outputs on external bus pins • PPM (peripheral pin multiplexing with parallel-to-serial driver) module • Available in package or die - Plastic ball grid array (PBGA) packaging