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MPC9658, MPC9658FA, MPC970L

Table of contents:
Info of MPC9658
Info of MPC9658FA
Info of MPC970L

MPC9658, MPC9658FA, MPC970L Selling Leads, Datasheet

MFG:Freescale Semiconductor Category:Integrated Circuits (ICs) Package Cooled:MOT D/C:04+

MPC9658, MPC9658FA, MPC970L Datasheet download

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Part Number: MPC9658

Category: Integrated Circuits (ICs)

MFG: Freescale Semiconductor

Package Cooled: MOT

D/C: 04+

Description: IC CLOCK GEN PLL LV 1:10 32-LQFP

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MPC9658 General Description

The MPC9658 is a 3.3V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250 MHz and output skews less than 120 ps the device meets the needs of the most demanding clock applications. The MPC9658 is specified for the temperature range of 0 to +70.

MPC9658 Maximum Ratings

Symbol	Characteristics	Min	Max	Unit	Condition
V_CC	Supply Voltage	-0.3	3.9	V
V_IN	DC Input Voltage	-0.3	V_CC+0.3	V
V_OUT	DC Output Voltage	-0.3	V_CC+0.3	V
I_IN	DC Input Current		±20	mA
I_OUT	DC Output Current		±50	mA
T_S	Storage Temperature	-65	125

a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.

MPC9658 Features

• 1:10 PLL based low-voltage clock generator
• Supports zero-delay operation
• 3.3V power supply
• Generates clock signals up to 250 MHz
• Maximum output skew of 120 ps
• Differential LVPECL reference clock input
• External PLL feedback
• Drives up to 20 clock lines
• 32 lead LQFP packaging
• Pin and function compatible to the MPC958

MPC9658 Typical Application

·The MPC9658 supports output clock frequencies from 50 to 250 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges are supported: 50 to 125 MHz and 100 to 250 MHz. Table 7 illustrates the configurations supported by the MPC9658. PLL zero-delay is supported if BYPASS=1, PLL_EN=1 and the input frequency is within the specified PLL reference frequency range.

MPC9658 Connection Diagram

MPC9658FA Parameters

Technical/Catalog Information	MPC9658FA
Vendor	Freescale Semiconductor
Category	Integrated Circuits (ICs)
Type	PLL Clock Generator
Voltage - Supply	3.135 V ~ 3.465 V
Number of Outputs	10
Input	LVCMOS, LVPECL
Output	LVCMOS
Frequency-Max	250MHz
Package / Case	32-LQFP
Packaging	Tray
Operating Temperature	0°C ~ 70°C
Drawing Number	375; 873A-03; FA; 32
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	MPC9658FA MPC9658FA

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