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The NL17SZ07 is a high performance single inverter with open drain outputs operating from a 1.65 to 5.5 V supply.
The Output stage is open drain with Over Voltage Tolerance. This allows the NL17SZ07 to be used to interface 5.0 V circuits to circuits of any voltage between 0 and +7.0 V.
NL17SZ07 Maximum Ratings
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
−0.5 to + 7.0
V
VI
DC Input Voltage
−0.5 VI +7.0
V
VO
DC Output Voltage Output in Higher or Low State (Note 1)
−0.5 VO +7.0
V
IIK
DC Input Diode Current VI < GND
−50
mA
IOK
DC Output Diode Current VO = GND VO = VCC
−50
mA
IOU
DC Output Sink Current
±50
mA
ICC
DC Supply Current per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
PD
Power Dissipation in Still Air SOT-353 SOT-553
186 135
°C
JA
Thermal Resistance SOT- 353 SOT- 553
350 496
°C/W
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
ILatch−Up
Latch−Up Performance Above VCC and Below GND at 85°C (Note 5)
+500
MSL
Moisture Sensitivity
Level 1
FR
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
VESD
ESD Classification Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5)
Class IC Class A N/A
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A, rated to EIA/JESD22−A114−B. 3. Tested to EIA/JESD22−A115−A, rated to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78.
NL17SZ07 Features
• Tiny SOT−353 and SOT−553 Packages • Extremely High Speed: tPD 2.5 ns (typical) at VCC = 5 V • Designed for 1.65 V to 5.5 V VCC Operation, CMOS Compatible • Over Voltage Tolerant Inputs VIN may be Between 0 and 7.0 V for VCC Between 0.5 and 5.4 V • TTL Compatible − Interface Capability with 5.0 V TTL Logic with VCC = 2.7 V to 3.6 V • LVCMOS Compatible • 24 mA Output Sink Capability, Pullup may be between 0 and 7.0 V • Near Zero Static Supply Current Substantially Reduces System Power Requirements • Chip Complexity: FET = 20 • Pb−Free Packages are Available