PM8353, PM8353-PC-BP, PM8353-PC-CP Selling Leads, Datasheet
MFG:PMC Package Cooled:N/A D/C:08+
PM8353, PM8353-PC-BP, PM8353-PC-CP Datasheet download
Part Number: PM8353
MFG: PMC
Package Cooled: N/A
D/C: 08+
PM8353, PM8353-PC-BP, PM8353-PC-CP
- Table of contents:
Info of PM8353
Info of PM8353-PC-BP
Info of PM8353-PC-CP
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About PM8353
PDF/DataSheet Download
Datasheet: PM8353
File Size: 125647 KB
Manufacturer: PMC [PMC-Sierra, Inc]
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About PM8
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Datasheet: PM8
File Size: 118464 KB
Manufacturer:
Download : Click here to Download
About PM8
PDF/DataSheet Download
Datasheet: PM8
File Size: 118464 KB
Manufacturer:
Download : Click here to Download
PM8353 General Description
The QuadPHYTM is a Quad PHYsical ayer transceiver ideal for systems equiring large numbers of point-to-point igabit links. It provides four individual erial channels capable of operation at p to 1.25 Gbps each, which may be rouped together to form a single 5.0 bps bidirectional link. Each of the four rimary channels has a corresponding econdary channel that can be enabled ia the MDC/MDIO serial interface.
The QuadPHY includes 8B/10B block oding logic (compliant with 802.3z igabit Ethernet and Fibre Channelrequirements) which produces run length imited data streams for serial transmission.
A receive FIFO optionally aligns all incoming parallel data to the local clock domain, adding or removing IDLE equences as required. This simplifies mplementation of the upstream ASIC by emoving the requirement to deal with ultiple clock domains.
When trunking is enabled, the QuadPHY an remove cable skew differences quivalent to several meters, presenting -byte data vectors at the receive nterface exactly as they were transmitted
PM8353 Features
• Four independent 1.0-1.25 Gbit/s ransceivers
• Four secondary channels to support hannel redundancy
• Ultra low power operation: 1.25 Watt ypical
• Integrated serializer/deserializer, clock ynthesis, clock recovery, and 8B/10B ncode/decode logic
• Physical Coding Sublayer (PCS) logic or Gigabit Ethernet
• Selectable 8-bit, 10-bit, or IEEE 802.3z MII parallel interface
• Optional Receive FIFOs which ynchronize incoming data to local lock domain
• "Trunking" feature to de-skew and lign received parallel data across four hannels
• 100-156 MHz Single Data Rate (SDR) arallel transmit interface with clock orwarding
• 100-125 MHz SDR parallel receive nterface
• Extensive control of loopback, BIST, nd operating modes via 802.3 ompliant MDC/MDIO serial interface
• Built-in packet generator/checker
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and NSI X3T11 Fibre Channel support
• High speed outputs which feature rogrammable output current to irectly drive dual-terminated line
• 2.5V, 0.25 micron CMOS technology ith 3.3V tolerant I/O
• Direct interface to optical modules, oax, or serial backplanes
• Small footprint 19x19 mm, 289-pin BGA
PM8353 Typical Application
• High speed serial backplanes
• Gigabit Ethernet links
• Fibre Channel links
• Intra-system interconnect
• ASIC to PMD link
• Gigabit Ethernet links
• Fibre Channel links
• Intra-system interconnect
• ASIC to PMD link
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