RS6MC-NL, RS701, RS702 Selling Leads, Datasheet
MFG:80000 Package Cooled:FAIRCHILD D/C:07+
RS6MC-NL, RS701, RS702 Datasheet download
Part Number: RS6MC-NL
MFG: 80000
Package Cooled: FAIRCHILD
D/C: 07+
RS6MC-NL, RS701, RS702
- Table of contents:
Info of RS6MC-NL
Info of RS701
Info of RS702
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About RS601
PDF/DataSheet Download
Datasheet: RS601
File Size: 175752 KB
Manufacturer: MCC [Micro Commercial Components]
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About RS701PC
PDF/DataSheet Download
Datasheet: RS701PC
File Size: 410320 KB
Manufacturer:
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About RS702PC
PDF/DataSheet Download
Datasheet: RS702PC
File Size: 410320 KB
Manufacturer:
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RS701 General Description
The RS701 has the following features including Serial data rates up to 3 Gbits/sec;16-bit wide ECL-compatible parallel data I/O;Advanced HBT GaAs process yields high margins and very fast edge rates;High speed differential serial data I/O and clock inputs (optionally single-ended);Fully differential internal logic minimises skew and fitter.
The RS701 Mux is parallel-to-serial and serial-to-parallel digital data conversion IC capable of serial rates up to 3 Gbits/sec. rabricated using Rockwell's advanced A1GaAs/GaAs HBT (heterojunction bipolar transistor) process, these devices provide high speed coupled with low power dissipation. All internal logic is differential to minimize signal skew and fitter. High speed data and clock signals are also differential, but may be used single-ended. To ease system design, both devices use industry standard power supplies and ECL-compatible I/Os for parallel data. These devices are ideal for applications including fiber optic communications, data transmission,test equipment, and instrumentation.The RS701 contains a 16-to-1 mux, a phase comparator,and a timing circuit which generates a divide-by-16 clock from the high speed clock input. The 16-to-1 mux accepts 16 parallel single-ended ECL compatible inputs (D0 through D15) and serializes them bitwise into data stream present at output DO/DON.
The RS701's internal phase comparator monitors the relationship between the internally generated divide-by-16 clock and an eternally supplied low speed reference clock input DCLK/DCLKN. Phase differences detected between these two clock signals in the phase comparator will generate an up or down output (U, D) for phase lock applications. Using the U and D signals, the phase comparator can be used as part of an external phase-locked loop (PLL) to perform a clock multiplication function.In applications that can provide a high speed system clock and do not require the phase comparator, the DCLK input should be connected to VTT through a 50 ohm resistor. The U and D outputs can be left unconnected.
RS701 Maximum Ratings
RS701 Features
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