RTL8305S, RTL8305SB, RTL8305SB-LF Selling Leads, Datasheet
MFG:REALTEK Package Cooled:QFP-128 D/C:05+
RTL8305S, RTL8305SB, RTL8305SB-LF Datasheet download
Part Number: RTL8305S
MFG: REALTEK
Package Cooled: QFP-128
D/C: 05+
RTL8305S, RTL8305SB, RTL8305SB-LF
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Info of RTL8305S
Info of RTL8305SB
Info of RTL8305SB-LF
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About RTL8305S
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Datasheet: RTL8305S
File Size: 427270 KB
Manufacturer: ETC [ETC]
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About RTL8305SB
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Datasheet: RTL8305SB
File Size: 986994 KB
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About RTL035N03
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Datasheet: RTL035N03
File Size: 82850 KB
Manufacturer: ROHM
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RTL8305S General Description
The RTL8305S is a highly integrated layer 2 single chip switch controller which incorporates 5 MACs (Media Access Controller), 5 physical layer transceivers, 1-Mbit SRAM and 1K-entry look-up table into one single chip.
The RTL8305S contains 5 ports, and each one provides support for a 10Base-T (10Mbps) or 100Base-TX (100Mbps) network connection. The fifth port (port 4) can be configured as a MII/SNI to work with a routing engine, HomePHY or a fiber transceiver for a 100Base-FX application. And each operation mode can be easily set up by hardware strapping upon restart or power-on.
The RTL8305S is designed for a stand-alone switch system through hardware strapping upon reset to achieve unmanaged operation and can be easily integrated with xDSL/Cable modem router. With the least peripheral components and using a 25MHz crystal, the RTL8305S has the best system cost structure. The integrated RTL8305S chip benefits from low power consumption and ease of use for SOHO 5-port switch or xDSL/Cable router applications.
RTL8305S Maximum Ratings
| Parameter | Min | Max | Units |
| Storage Temperature | -45 | +125 | °C |
| Vcc Supply Referenced to GND | -0.5 | +4.0 | V |
| Digital Input Voltage | -0.5 | Vcc | V |
| DC Output Voltage | -0.5 | Vcc | V |
RTL8305S Features
· 5-port integrated switch with physical layer and transceiver for 10Base-T and 100Base-TX with 5-port 10/100M UTP or 4-port 10/100M UTP + 1-port MII/SNI
· PHY mode MII/SNI interface for router application
· MAC mode MII interface for HomeLAN/100Base-FX application
· 1Mbit internal RAM for packet buffer
·Internal 1K look-up table entries
· 25MHz crystal or OSC input
· Non-blocking wire-speed reception and transmission
· Fully compliant with IEEE 802.3/802.3u
· Supports broadcast storm filtering function
· Support full duplex 802.3x flow control and half duplex back-pressure flow control
· LED indicators for link/activity, speed, full/half duplex and collision
· LEDs blinking upon reset for LED diagnostics
· Unmanaged operation by strapping upon reset
· Power saving with cable detection
· Low power consumption at 3.3V operating voltage
· 128-pin PQFP package
· PHY mode MII/SNI interface for router application
· MAC mode MII interface for HomeLAN/100Base-FX application
· 1Mbit internal RAM for packet buffer
·Internal 1K look-up table entries
· 25MHz crystal or OSC input
· Non-blocking wire-speed reception and transmission
· Fully compliant with IEEE 802.3/802.3u
· Supports broadcast storm filtering function
· Support full duplex 802.3x flow control and half duplex back-pressure flow control
· LED indicators for link/activity, speed, full/half duplex and collision
· LEDs blinking upon reset for LED diagnostics
· Unmanaged operation by strapping upon reset
· Power saving with cable detection
· Low power consumption at 3.3V operating voltage
· 128-pin PQFP package
RTL8305S Connection Diagram
RTL8305SB General Description
The RTL8305SB is a Fast Ethernet switch, which integrates memory, five MACs, and five physical layer transceivers for
10Base-T and 100Base-TX operation into a single chip. All ports support 100Base-FX, which share pins (TX+-/RX+-) with UTP ports and need no SD+/- pins, a development using Realtek proprietary technology. Due to the lack of auto-negotiation in 100Base-FX applications, the RTL8305SB can be forced into half or full duplex mode and can enable or disable flow control in fiber mode.
The five ports are separated into 3 groups (GroupX/GroupY/Port4) for flexible port configuration using strapping pins upon reset. The SetGroup pin is used to select port members in GroupX and GroupY. While the port members is determined, you can use mode selection pin (GxMode/Gymode/P4Mode[1:0]) to select operating interfaces such as 10/100Base-TX, 100Base-FX. Each group has 4 pins to select initial port status (ANEG/Force, 100/10, Full/Half, Enable/Disable Flow Control) upon reset. Upon reset, in addition to using strapping pins, the RTL8305SB also can be configured with an EEPROM or read/write operation by a CPU through the MDC/MDIO interface.
The fifth port (port 4) supports an external MAC interface, which can be set to PHY mode MII, PHY mode SNI, or MAC
mode MII to work with a routing engine, HomePNA or VDSL transceiver. In order to accomplish diagnostics in complex
network systems, the RTL8305SB also provides a loopback feature in each port for a variable CPU system.
The RTL8305SB contains a 1K entry address look-up table and supports a 16 entry CAM to avoid hash collisions and to maintain forwarding performance. The RTL8305SB supports IEEE 802.3x full duplex flow control and back- pressure half duplex flow control. The broadcast storm filtering function is provided to filter unusual broadcast storm issues and has an intelligent switch engine to prevent Head-Of -Line blocking problems.
The RTL8305SB supports 5 groups of VLANs which can be configured with port based VLAN and/or 802.1Q tag VLAN.
ARP broadcast and Leaky VLAN are also supported for advanced applications.
The RTL8305SB supports several types of QoS functions with two level priority queues to improve multi-media or real-time networking applications. The QoS functions are based on: 1) Port based priority; 2) 802.1Q VLAN priority tag; 3) The TOS/DS (DiffServ) field of TCP/IP. In order to avoid the flow control function effecting the quality of high priority frames, the RTL8305SB supports an intelligent flow control for high priority frames by setting DisFCAutoOff to automatically turn off flow control for 1~2 seconds whenever the congestion port receives high priority frames. When the QoS function is enabled, a VLAN tag can be inserted or removed at the output port. The RTL8305SB will insert a VLAN priority-tag (VID=0x000) for untagged frames or remove the tag for all tagged frames.
Maximum packet length can be 1536 or 1552 bytes according to the initial configuration (strapping upon reset). The filtering function is supported for the 802.1D specified reserved group MAC addresses (01-80-C2-00-00-03 to 01-80-C2-00-00-0F).
The RTL8305B provides flexible LED functions for diagnostics, which include: 1) Four combinations of link, activity, speed, duplex and collision which are designed for convenient LED displays, such as bi-color LEDs; 2) Reset blinking; 3) Blinking time selection. The RTL8305SB also provides a loop detection function and alarm, for network existence notification, with an output pin which can be designed as a visual LED or a status input pin for a CPU.
The RTL8305SB implements a power saving mode on a per port basis. One port automatically enters power saving mode 10 seconds after the cable is disconnected from it. The RTL8305SB also implements a power down mode on a per port basis.
Users can set MII Reg.0.11 to force the corresponding port to enter the power down mode, which disables all transmit/receive functions, except SMI (MDC/MDIO management interface).
Each physical layer channel of the RTL8305SB consists of a 4B5B encoder/decoder, a Manchester encoder/decoder, a
scrambler/descrambler, a transmit output driver, output wave shaping filters, a digital adaptive equalizer, a PLL circuit and a DC restoration circuit for clock/data recovery. Friendly crossover auto detection and correction functions are also supported for easy cable connection.
The integrated chip benefits from low power consumption, advanced functions with flexible configurations for 5-port SOHO switch, Home Gateway, xDSL/Cable router, and other IA applications.
RTL8305SB Maximum Ratings
| Parameter | Min | Max | Units |
| Storage Temperatur | -55 | +150 | °C |
| Vcc Supply Referenced to GND | -0.5 | +4.0 | V |
| Digital Input Voltage | -0.5 | VDD | V |
| DC Output Voltage | -0.5 | v | V |
RTL8305SB Features
` 5-port integrated switch controller with memory and transceiver for 10Base-T and 100Base-TX with
` 5-port 10/100M UTP or
` 4-port 10/100M UTP + 1-port MII/SNI
` Supports PHY mode MII /SNI for router applications and MAC mode MII for HomePNA or VDSL solutions
` All ports support 100Base-FX with optional flow control enable/disable and full/half duplex setting
` Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding
` Fully compliant with IEEE 802.3/802.3u auto-negotiation function
` Built-in high efficiency SRAM for packet buffer and 1K entry look-up table, and 16 entry CAM
` Supports broadcast storm filtering function
` Supports IEEE802.3x full duplex flow control and back pressure half duplex flow control
` Supports SMI (Serial Management Interface: MDC/MDIO) for programming and diagnostics
` Supports loop detection function with one LED to indicate the existence of loop
` Supports loopback function for diagnosis
` Flexible 802.1Q Port based VLAN. Up to 5 VLAN
`Supports 802.1Q tag VLAN function
` Supports ARP VLAN for broadcast packets
` Supports Leaky VLAN for unicast packets
` Supports QoS function on each port:
` QoS based on: (1) Port-based (2) VLAN tag (3) TCP/IP header's TOS/DS
` Supports two level priority queues
`Weighted round robin service
` Supports VLAN priority tag Insert/Remove function
` Optional 1536 or 1552 byte maximum packet length
` Supports reserved control frames (DID= 0180C2000003~0180C200000F) filtering function
` Flexible LED indicators for link, activity, speed, full/half duplex and collision
` LEDs blink upon reset for LED diagnostics
` Supports two Power Reduction methods:
` Power saving mode by cable detection
` Power down mode (by PHY register 0.11)
` Robust baseline wander correction for improved 100BASE-TX performance
` Optional Crossover Detection and Auto Correction function
` Physical layer port Polarity Detection and Correction function
` Optional EEPROM interface for configuration
` 25MHz crystal or OSC input. Single 3.3V power system like by translating of an external transistor
` 0.25 m, CMOS technology, 3.3V/2.5V with 3.3V input tolerant, 128 pin PQFP package
` 5-port 10/100M UTP or
` 4-port 10/100M UTP + 1-port MII/SNI
` Supports PHY mode MII /SNI for router applications and MAC mode MII for HomePNA or VDSL solutions
` All ports support 100Base-FX with optional flow control enable/disable and full/half duplex setting
` Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding
` Fully compliant with IEEE 802.3/802.3u auto-negotiation function
` Built-in high efficiency SRAM for packet buffer and 1K entry look-up table, and 16 entry CAM
` Supports broadcast storm filtering function
` Supports IEEE802.3x full duplex flow control and back pressure half duplex flow control
` Supports SMI (Serial Management Interface: MDC/MDIO) for programming and diagnostics
` Supports loop detection function with one LED to indicate the existence of loop
` Supports loopback function for diagnosis
` Flexible 802.1Q Port based VLAN. Up to 5 VLAN
`Supports 802.1Q tag VLAN function
` Supports ARP VLAN for broadcast packets
` Supports Leaky VLAN for unicast packets
` Supports QoS function on each port:
` QoS based on: (1) Port-based (2) VLAN tag (3) TCP/IP header's TOS/DS
` Supports two level priority queues
`Weighted round robin service
` Supports VLAN priority tag Insert/Remove function
` Optional 1536 or 1552 byte maximum packet length
` Supports reserved control frames (DID= 0180C2000003~0180C200000F) filtering function
` Flexible LED indicators for link, activity, speed, full/half duplex and collision
` LEDs blink upon reset for LED diagnostics
` Supports two Power Reduction methods:
` Power saving mode by cable detection
` Power down mode (by PHY register 0.11)
` Robust baseline wander correction for improved 100BASE-TX performance
` Optional Crossover Detection and Auto Correction function
` Physical layer port Polarity Detection and Correction function
` Optional EEPROM interface for configuration
` 25MHz crystal or OSC input. Single 3.3V power system like by translating of an external transistor
` 0.25 m, CMOS technology, 3.3V/2.5V with 3.3V input tolerant, 128 pin PQFP package
RTL8305SB Connection Diagram
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