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RTL8308B, RTL8309, RTL8309SB

Table of contents:
Info of RTL8308B
Info of RTL8309
Info of RTL8309SB

RTL8308B, RTL8309, RTL8309SB Selling Leads, Datasheet

MFG:REALTEK Package Cooled:QFP D/C:07+

RTL8308B, RTL8309, RTL8309SB Datasheet download

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Part Number: RTL8308B

MFG: REALTEK

Package Cooled: QFP

D/C: 07+

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RTL8308B General Description

The RTL8308B is a 128-pin, low cost and ultra low power consumption 8-port 10/100M Ethernet switch controller. It is integrated both with a 2M bit embedded DRAM, as a packet buffer, and an 8K entry address table.

The RTL8308B supports the reduced MII (RMII) interface. Only a single 50MHz oscillator is needed and the EEPROM is optional, which can save BOM costs. In addition, the RTL8308B provides an LED display to indicate a network loop existence.

The RTL8308B provides eight 10/100 Mbps RMII Ethernet ports. Each port can operate in 10 Mbps or 100 Mbps data rate, and in full or half duplex mode. Speed, duplex, link status and flow control can be acquired by periodically polling the status of the PHY devices via MDIO.

The address look-up table consists of an 8K entry hash table and a 128 entry CAM. The RTL8308B uses the address hashing algorithm or direct mapping method to search destination MAC addresses from and record source MAC addresses to the hash table. Data received from the MAC interface is stored in the external memory buffer.

The RTL8308B supports IEEE 802.3x full duplex flow control and half duplex back pressure control. The ability of IEEE 802.3x flow control is auto-negotiated by writing the flow control ability via MDIO. The reversible PHYAD order feature is provided to connect diverse external PHY devices for PCB layout.

The RTL8308B provides a loop detect LED for visual diagnostics when detecting the network loop. The Broadcast storm filtering function is provided for unusual broadcast storm traffic.

The RTL8308B supports non-blocking 148800 packets/second wire speed forwarding rate and a special design to resolve the head-of-line-blocking problem. The RTL8308B uses a 2-wire 24LC02 interface to access the external serial EEPROM, which is not required. Only one 50MHz OSC is needed.

RTL8308B Features

· Supports eight 10/100Mbps Ethernet ports with
    RMII interface
· Provides forwarding of non-blocking and
    non-head-of-line-blocking
· 2M bit DRAM built in as a packet storage buffer
· Page based buffer management to efficiently
    utilize the internal packet buffer
· Ultra low power consumption with less than
    160mA at 3.3V operating voltage
· Embedded 8K entry look-up table and 128 entry
    CAM
· Supports address hashing or direct mapping for
     look-up table
· 128-entry CAM is used to eliminate the hash
    collision issues
· Supports full and half duplex operation
· Link, speed and duplex status are auto-detected via
    MDIO
· Broadcast storm control
· Flow control fully supported:
         · Half-duplex: back pressure
         ·Full-duplex: IEEE 802.3X
· Auto-negotiated Full-duplex flow control by
     writing the ability via MDIO to external PHY
· Supports Store-and-forward and cut-through
     operation
· Provides an LED display to indicate network loop
     existence
· Reversible PHYAD order for diverse PHY usage
· 3.3V 24LC02 interface
· Optional EEPROM 24LC02 for Loop detect
configuration
· 128-pin PQFP, 0.35 um, 3.3V CMOS technology

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