S3024, S30247S2-1, S3024A/TD Selling Leads, Datasheet
MFG:2000 Package Cooled:ssop- D/C:AMCC
S3024, S30247S2-1, S3024A/TD Datasheet download
Part Number: S3024
MFG: 2000
Package Cooled: ssop-
D/C: AMCC
S3024, S30247S2-1, S3024A/TD
- Table of contents:
Info of S3024
Info of S30247S2-1
Info of S3024A/TD
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About S3024
PDF/DataSheet Download
Datasheet: S3024
File Size: 260359 KB
Manufacturer: Applied Micro Circuits Corporation
Download : Click here to Download
About S3005
PDF/DataSheet Download
Datasheet: S3005
File Size: 127047 KB
Manufacturer: Applied Micro Circuits Corporation
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About S3005
PDF/DataSheet Download
Datasheet: S3005
File Size: 127047 KB
Manufacturer: Applied Micro Circuits Corporation
Download : Click here to Download
S3024 General Description
The function of the S3024 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3024 is implemented using AMCC's proven Phase Locked Loop (PLL) technology.
The S3024 receives either an OC-12/STM-4 or OC-3/ STM-1 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential LVPECL bit clock and retimed data. Figure 1 shows a typical network application.
The S3024 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2.
S3024 Maximum Ratings
| Parameter | Min | Typ | Max | Units |
| Storage Temperature | -65 | 150 | °C | |
| Voltage on VCC with Respect to GND | -0.5 | +7.0 | V | |
| Voltage on any LVTTL Input Pin | -0.5 | VCC | V | |
| Voltage on any LVPECL Input Pin | V CC 2.0 |
VCC | V | |
| LVTTL Output Sink Current | 20 | mA | ||
| LVTTL Output Source Current | 10 | mA | ||
| High Speed LVPECL Output Source Current | 50 | mA |
S3024 Features
• Complies with Bellcore and ITU-T
specifications for jitter tolerance, jitter transfer
and jitter generation
• On-chip high frequency PLL with internal loop
filter for clock recovery
• Supports clock recovery for OC-12/STM-4
(622.08 Mbit/s) or OC-3/STM-1 (155.52 Mbit/s) NRZ data
• 19.44 MHz reference frequency
• Lock detect-monitors frequency
• 264 mW typical power dissipation
• Low-jitter LVPECL interface
• Maintains downstream clock in absence of data inputs
• 3.3V supply
• Available in a 20 pin TSSOP package
• Active High LVPECL Signal Detect
specifications for jitter tolerance, jitter transfer
and jitter generation
• On-chip high frequency PLL with internal loop
filter for clock recovery
• Supports clock recovery for OC-12/STM-4
(622.08 Mbit/s) or OC-3/STM-1 (155.52 Mbit/s) NRZ data
• 19.44 MHz reference frequency
• Lock detect-monitors frequency
• 264 mW typical power dissipation
• Low-jitter LVPECL interface
• Maintains downstream clock in absence of data inputs
• 3.3V supply
• Available in a 20 pin TSSOP package
• Active High LVPECL Signal Detect
S3024 Connection Diagram
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