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S3025, S3026, S3026A TSSOP20 250 AMCC 2005+ -

Table of contents:
Info of S3025
Info of S3026
Info of S3026A TSSOP20 250 AMCC 2005+ -

S3025, S3026, S3026A TSSOP20 250 AMCC 2005+ - Selling Leads, Datasheet

MFG:2000 D/C:AMCC

S3025, S3026, S3026A TSSOP20 250 AMCC 2005+ - Picture

S3025, S3026, S3026A TSSOP20 250 AMCC 2005+ - Datasheet download

Five Points

Part Number: S3025

MFG: 2000

Package Cooled:

D/C: AMCC

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S3025 General Description

The function of the S3025 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3025 is implemented using AMCC's proven Phase Locked Loop (PLL) technology.

The S3025 receives an OC-12/STM-4 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential PECL bit clock and retimed data.

The S3025 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2.

S3025 Maximum Ratings

Parameter	Min	Typ	Max	Units
Case Temperature under Bias	-55		+125	°C
Junction Temperature under Bias	-55		+150	°C
Storage Temperature	-65		+150	°C
Voltage on VCC with Respect to GND	-0.5		+7.0	V
Voltage on any LVTTL Input Pin	-0.5		V_CC	V
Voltage on any LVPECL Input Pin	V _CC 2.0		V_CC	V
TTL Output Sink Current			20	mA
TTL Output Source Current			10	mA
High Speed LVPECL Output Source Current			50
Static Discharge Voltage		500		mA

S3025 Features

• Complies with ANSI, Bellcore, and ITU-T
specifications for jitter tolerance,
   jitter transfer and jitter generation
• On-chip high frequency PLL with internal
   loop filter for clock recovery
• Supports clock recovery for OC-12/STM-4
   (622.08 Mbit/s) NRZ data
• 12.96 MHz reference frequency
• Lock detect-monitors run length and frequency
• 350mW typical power dissipation
• Low-jitter PECL interface
• On-chip crystal oscillator allows use of low cost reference crystal
• Micro-power Bipolar technology
• 5V supply
• Available in die form or 20 TSSOP package

S3026 General Description

The function of the S3026 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3026 is implemented using AMCC's proven Phase Locked Loop (PLL) technology.

The S3026 receives either an OC-12/STM-4 or OC-3/ STM-1 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential PECL bit clock and retimed data. Figure 1 shows a typical network application.

The S3026 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts

S3026 Maximum Ratings

Parameter	Min	Typ	Max	Units
Storage Temperature	-65		+150	°C
Voltage on VCC with Respect to GND	-0.5		+7.0	V
Voltage on any LVTTL Input Pin	-0.5		+5.5	V
Voltage on any LVPECL Input Pin	V CC 2.0		V_CC	V
TTL Output Sink Current			20	mA
TTL Output Source Current			10	mA
High Speed LVPECL Output Source Current			50	mA
ESD Sensitivity 1	Under500			V

S3026 Features

• Complies with Bellcore and ITU-T
   specifications for jitter tolerance, jitter transfer
   and jitter generation
• On-chip high frequency PLL with internal loop
   filter for clock recovery
• Supports clock recovery for OC-12/STM-4
   (S3026A) (622.08 Mbit/s) or
   OC-3/STM-1 (155.52 Mbit/s) (S3026A-1) NRZ data
• 19.44 MHz reference frequency
• Lock detect-monitors run length (S3026A only) and frequency
• 350 mW typical power dissipation
• Low-jitter PECL interface
• Maintains downstream clock in absence of data inputs
• Micro-power Bipolar technology
• 5V supply
• Available in a 20 TSSOP package

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