S3028B, S3029, S3029A Selling Leads, Datasheet
MFG:AMCC Package Cooled:N/A D/C:1500
S3028B, S3029, S3029A Datasheet download
Part Number: S3028B
MFG: AMCC
Package Cooled: N/A
D/C: 1500
S3028B, S3029, S3029A
- Table of contents:
Info of S3028B
Info of S3029
Info of S3029A
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About S3028B
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Datasheet: S3028B
File Size: 171917 KB
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About S3029
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Datasheet: S3029
File Size: 88708 KB
Manufacturer: Applied Micro Circuits Corporation
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About S3005
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Datasheet: S3005
File Size: 127047 KB
Manufacturer: Applied Micro Circuits Corporation
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S3029 General Description
The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment. The S3029 is implemented using AMCC's proven Phase Locked Loop (PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock. The chip outputs a differential PECL bit clock and retimed data. Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2. There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input.
S3029 Maximum Ratings
| Parameter | Min | Typ | Max | Units |
| Ambient Temperature under Bias (industrial) | -40 | +85 | °C | |
| Ambient Temperature under Bias (commercial) | 0 | +70 | °C | |
| Junction Temperature under Bias | 10 | +130 | °C | |
| Voltage on VCC with Respect to GND | 3.14 | 3.3 | 3.46 | V |
| Voltage on any LVTTL Input Pin | 0.0 | VCC | V | |
| Voltage on any LVPECL Input Pin | V CC2 | VCC | V | |
| PECL Output Source Current (50Wto Vcc-2V) | 14 | 25 | mA | |
| ICC Supply Current | 225 | 276 | mA |
S3029 Features
• Complies with ANSI, Bellcore, and ITU-T
specifications for jitter tolerance, jitter generation
• Five on-chip high frequency PLLs with
internal loop filters for clock recovery
• Supports clock recovery for STS-3/STM-1
(155.52 Mbit/s) NRZ data
• Clock Multiplier PLL for transmit clock generation
• 19.44 or 51.84 MHz reference frequency
• Lock detect-monitors run length and frequency
• Low-jitter differential interface
• 3.3V supply
• Available in a 64-pin TQFP package
• Compatible with IgT WAC-413 ATM Quad- UNI processor
specifications for jitter tolerance, jitter generation
• Five on-chip high frequency PLLs with
internal loop filters for clock recovery
• Supports clock recovery for STS-3/STM-1
(155.52 Mbit/s) NRZ data
• Clock Multiplier PLL for transmit clock generation
• 19.44 or 51.84 MHz reference frequency
• Lock detect-monitors run length and frequency
• Low-jitter differential interface
• 3.3V supply
• Available in a 64-pin TQFP package
• Compatible with IgT WAC-413 ATM Quad- UNI processor
S3029 Connection Diagram
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